AD7175-8 Using Single Ended Inputs - Only able to read Odd Numbered Channels

Dear EngineerZone community,

The device presenting an issue is AD7175-8 interfaced to an Atmel Sam4S via SPI communications.  It is configured to read single ended data from channels 0 through 9 at a sample rate of 59.9Hz. 

All channels use the same Setup_Config_0 configured as 0x0300 => Unipolar, AINBUF+ enabled, External Reference.  Filter_Config_0 is configured as 0x020F => Sinc3, 59.92 S/s  

Offset and Gain are unchanged from default.

A read of all channels 0 through 9, along with respective status byte for each channel, indicates only odd number channel acquisition data are being read.  Modifying the code to only read even channels results in odd channel data read back. 

Having read back the setup registers over SPI, fairly confident the setup is correct:  

Read Ch 0 Map, now 0x8016  // channel enabled
Read Ch 1 Map, now 0x0036  // channel disabled
Read Ch 2 Map, now 0x8056
Read Ch 3 Map, now 0x0076
Read Ch 4 Map, now 0x8096
Read Ch 5 Map, now 0x00b6
Read Ch 6 Map, now 0x80d6
Read Ch 7 Map, now 0x00f6
Read Ch 8 Map, now 0x8116
Read Ch 9 Map, now 0x0136
Read Ch 10 Map, now 0x0156
Read Ch 11 Map, now 0x0176

Whether continually reading or performing a read on just a single channel, the status byte received with the data indicates an odd numbered channel. 

Status Byte (I know it indicates an ADC_ERROR.  This is due to no input voltage, inputs float to small negative V.)



47 A/D conversion, now 0.000000
43 A/D conversion, now 0.000000
49 A/D conversion, now 0.000000
45 A/D conversion, now 0.000000
49 A/D conversion, now 0.000000
43 A/D conversion, now 0.000000
49 A/D conversion, now 0.000000
45 A/D conversion, now 0.000000
41 A/D conversion, now 0.000000

Modification of the code to only read channel 0 results in readback with status byte indicating channel 1.

Thank you for any advice and/or direction.


  • While the logic analyzer traces look good and the return Status Byte is interpreted correctly, the oscilloscope revealed signal integrity issues on the clock near the processor.  The sclk is being delayed with respect to miso.  This didn't show up on other register reads  because miso would typically go low after transmitting the last byte.  In the case of reading data and status, miso goes high after the last byte (status) is clocked.  This high level, due to signal degradation, is clocked in as the last bit.  This turns channel address 0 into address 1.

    Possibly need some series resistance in the clock line for impedance matching, to damp over/undershoot. 

  • The signal integrity issue was solved by disconnecting the SPI bus from a connector to the outside world.  I have a good 22ns of time between sclk LH and MISO at as data low for the LSBit before MISO going LH.  This time satisfies both ADC and SAM4S stated Tset and Thold.  Despite this, MISO is being clocked in as a high LSB on the status byte. 

    Here is a scope image of the Status byte being clocked in after the data is read.  Status should indicate channel 0, but is read as channel 1.

    The Fixx


    Careful reading of the datasheet, page 43 DOUT_RESET:    

    "After the read is complete, the pin reverts to outputting the RDY signal after a short fixed period of time (t 7 ). However, this time may be too
    short for some microcontrollers and can be extended until the CS pin is brought high by setting the DOUT_RESET bit in
    the interface mode register to 1. This means that CS must be used to frame each read operation and compete the serial
    interface transaction."

    Setting the DOUT_RESET bit in the Interface Mode Register remedied this issue!