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AD7176-2 has unknown noise in sample data.

Hi ADI,

I got EVAL-AD7176-2SDZ (Rev-A), and I use it to test audio signal.

I use AD7176-2 to sample a pure 12.5 kHz 0.1 Vrms sine wave, and sample rate is 125kHz.

But there is a stable low frequency noise as below picture, so it make the wave envelope is unstable.

I

My setting as below:

The attachment is my test data.

Do you have any idea about this problem?

Thanks.

Homeway

12.5kHz.csv.zip
  • Hi,

    May I ask for your input configurations? How did you connected your AC input voltage? Are you operating at single or dual supply? Can you also try to lower down the number of samples, let say try to make it 20 or just try to zoom in data to take a look at one or two cycles only. As I've seen the voltage values it looks like it swing to +/-140mV which is equivalent to your 0.1Vrms. Can you also checked your inputs at scope and compared it with the ADC results?

    Thanks,

    Jellenie

  • Hi,

    According to the nyquist theorem, the sampling rate must be at least twice the highest input frequency component. It states the minimum sampling rate to be able to replicate the signal, however, please take note that the higher the value of the sampling rate the closer the output to the expected results as you have more data points therefore the lesser the quantization error. Please take note also that the part requires a settling time at the very first conversion so it has different Tsettle at the first conversion and then the succeeding conversion will occur at the selected ODR.

    Thanks,

    Jellenie

  • Hi,

    Regarding the number of samples. Same thing can be applied to the number of samples, the minimum number of samples needed to replicate the signal is at least twice the ratio of your ODR/input frequency since the part needs the filter settling time at the very first conversion. Regarding the decrease in voltage, we have a  Virtual Eval on ADI site that may help you evaluate and understand the performance of the AD7176 with any signal frequency or configurations and settings you want. If you take a look at the filter profile of the said tool you will see the attenuation at your operating frequency. At 250ksps ODR, you have -0.15dB, at 125ksp you have -0.26db with12.5KHz input frequency. I think this tool will help you answer to your question.

    Thanks,

    Jellenie

  • Hi Jellenie,

    Thanks for your reply.

    May I ask for your input configurations?

    [Source : Audio precision AP515, single-end 12.5kHz 0.1Vrms sine-wave] 

    How did you connected your AC input voltage?C

    [connector J8 ,  AIN0 as AIN+, AIN1 as AIN- for channel 0]

    Are you operating at single or dual supply?

    [Single power supply for AD7176-2 J4, AVSS = -2.5V]  

    Can you also try to lower down the number of samples, let say try to make it 20 or just try to zoom in data to take a look at one or two cycles only. As I've seen the voltage values it looks like it swing to +/-140mV which is equivalent to your 0.1Vrms. Can you also checked your inputs at scope and compared it with the ADC results?

    [After check with scope, I find that if the sample rate is not enough, then the envelope is not fix.

    For 12.5kHz signal, sample rate should be more than 200 kHz, and capture data will be stable. 

    I am a little confused.

    According to Nyquist theorem, sample rate just need to twice as input signal frequency. 

    Why should I have to use sample rate that more than twice to get stable sample?]

    ==========================================================

    And I have a new question about AD7176-2 sample rate 250 kHz.

    Sample point # of 1 cycle = Sample rate / Signal frequency. =250 kHz / 12.5 kHz = 20

    But you can see below picture, I sample 40 points, but it seems have 3 cycles. 

    The problem only happens at sample rate 250 kHz.

    Could you help to check this issue?

     

    Thanks a lot.

    B.R.

    Homeway

     

     

  • Hi Jellenie,

    Understood.

    Thanks for your reply.

    So higher sample rate will make the result realize.

    But how about the problem about 250 kHs?

    I think the sample data frequency is 1.5 times more than input signal.

    And the voltage is also influenced by sample rate.

    Below is my measurement.

      

    You can see if sample rate decrease, then amplitude decrease, too.

    Thanks.

    B.R.

    Homeway

  • Hi Jellenie,

    Thanks for your reply.

    You are really kindly and patient.

    According to your tool Virtual Eval, I can get the real input voltage via compensate insertion loss.

    It is really awesome!

    ---------------------------------------------------------------------------------------

    Sorry that I don't understand your comment about sampling.

    Maybe my poor English let you confused.

    If I use sample rate 250 kHz, I will get wrong frequency of input signal. 

    For example, the input signal real frequency is 12.5 kHz, but if I use 250 kHz sample rate to capture it, then I will get the wrong frequency of input signal.

    But If I use the other setting of sample rate like 125 kHz, 50 kHz ..., I will get the right frequency of input signal.

    It is really strange. 

    Please help me to clarify this problem.

    --------------------------------------------------------------------------------------------------

    And I have one more question about below table.

    1. Why the noise increase with output data date?

    2. How to know the relative between effective resolution and noise?

    Is there any math equation?

    Could you share these knowledge with me?

    Thanks a lot.

    B.R.

    Homeway 

  • Hi,

    Have you tried to input other frequency and check if the reading with 250ksps ODR is also different?

    Regarding your questions:

    1. For sigma delta ADC, the signal is oversampled at a rate higher than the minimum required sampling rate (Nyquist frequency). This so called oversampling technique will spread the noise over a much wider bandwidth. The modulator has the added feature of noise shaping, wherein the quantization noise of the analog-to-digital conversion is shaped by the modulation scheme, shifting it (typically) from a low bandwidth up to a higher frequency, allowing a low-pass digital filter to eliminate it from the conversion result. There are two sampling rates to consider in this technique, the input sampling rate (modulator clock, Fmod) and the output data rate (digital/decimation filter's output data rate, ODR). The ratio between these two is called oversampling ratio (OSR). By reducing the filter's pass band and increasing the OSR, with the same sampling rate, Fmod, the lower data rates (blue) provide high effective resolutions as it has much lesser noise than the much higher data rate (green) as shown in the figure below. Hope this answer your question.

    2. The effective resolution is equal to the peak-peak resolution + 2.72. Peak to peak resolution  is determined from the noise value given in the datasheet. Please see equation below.

    wherein FS= Full scale range and p-p noise= 6.6 x RMS noise.

    Thanks,

    Jellenie

  • Hi Jellenie,

    [Have you tried to input other frequency and check if the reading with 250ksps ODR is also different?]

    Yes, I tried the other frequency, and they have the same problem, and the key point is 250ksps ODR.

    -----------Question about noise----------

    1. According to data sheet, Fmod is 8 MhZ. is it base on 16 MHz crystal?

    2. Why effective resolution have 2.72 bits benefit?

    3. Why p-p noise is  6.6 x RMS noise? Is it due to noise distribution?

     

    4. What is the frequency for Fmod/2? Below picture point A or B? 

    5. What is the slash line in the picture?

     

    B.R.

    Homeway 

  • Hi,

    May I know how many channels are enabled and have you enabled CRC and have you appended status to the data (i.e. Data+Status)? There is a limitation when using the SDP and running the ADC at the fastest output data rate. So please sure if any of the above feature was enable? Does an error also pop-up regarding SPI read limitation during your setup?

    1. Yes, the modulator clock 8MHz is from the master clock of 16MHz (crystal, internal or external) and it is internally divided.

    2. Because, effective resolution is calculated using rms noise rather than the p-p noise. Therefore, giving a value greater than p-p resolution by 2.72 bits.

    3. Yes, Figure 1 shows a typical histogram obtained from a sigma-delta ADC when the analog input is grounded.The rms noise is calculated using the curve that results from the histogram, the width of the curve determining the rms noise. A Gaussian curve goes from –infinity to +infinity. However, 99.99% of the codes occur within 6.6xrms noise.Therefore, the peak noise is 6.6xrms noise. 

    4. Point A looks like the -3dB frequency and point B is the ODR. The figure shows two sets of ODR, I just put these on the same figure just for you to see why the noise is lesser at lower ODR. This is just an example figure with no actual value.

    5. Yes, the line is the filter response. The steepness of the line will depends on the filter type.

    Thanks,

    Jellenie

  • Hi,

    Yes, that is true for the above error. Can you try to disable CRC and "Data+Status" if you will only use one channel.

    Thanks,

    Jellenie