AD7091R-8 Question

Hi

 

I have a question AD7091R-8.

 

【Question 1】
What happens to the conversion result if I repeat the above sequence during sequencer operation?
At this time, reset is not performed.

[Situation that is occurring]
Search result data is acquired with 0xFFF.
The Channel ID will be returned correctly.
There are no alerts.
Example: Return value of Channel 0 = 0x0FFF

【Question 2】
Settings other than Ox0CFF (Channel Register setting) and 0x00FF (Read command setting) and NOP are set for this device after startup.
For example, initial setting register setting etc is not set especially, but is there a problem?

 

 

Best Regards

HOD

  • 0
    •  Analog Employees 
    on Jan 10, 2018 1:08 AM

    Hi HOD,

    I'm a bit confused by the questions that you have asked.  The registers on the AD7091R-8 are circular registers.  The results can be read more than once.  Conversion results are not updated until a new conversion occurs.  Registers settings are not updated until new register settings are provided.  The current conversion results and registers settings can be continually read.

    Why are you using 0xFFF? The read command for reading the conversion result register is 0x00XX.

    If a sequencer setting is updated, the sequencer is reset.  This means that the next conversion will occur on the lowest enabled channel in the sequence.

    The channel register setting that you have provided in your question 2 will enable all channels on the AD7091R-8.  If the user does not write to the configuration register and all subsequent registers, the device will be configured with the default settings seen in the "Reset" column of tables 16 to 24.

    -- Ryan

  • Hi  Ryan

    Thnak you for your answer.

    【Items you would like to confirm】


    ① When starting each register at default by default
    Reset (both hardware and software) is not necessary.
     
    ②When reading / writing registers, be sure to assert * VOMVST
    It can not be read or written.
     
    ③ While AD conversion data is output to SDO, it is necessary to continue to give NOP to SDI.
    Since the AD conversion data is output later than the command, the same cycle that data after NOP comes out
    If register read commands are overlapped, SDO in that cycle is not output.
    SDI Channel (0X0CFF) → NOP → NOP → NOP · · · NOP → Channel Read
    SDO - → - → Channel 0 data → Channel 1 data · · · Channel 6 data → ❛ L fixed

     

    If you know , please teach me .

     

    Best Regards

    HOD

  • Hi

     

    Thank you for your answer.

     

    【Items you would like to confirm】

     

    ① When starting each register at default by default
    Reset (both hardware and software) is not necessary.
     
    ②When reading / writing registers, be sure to assert * VOMVST
    It can not be read or written.
     
    ③ While AD conversion data is output to SDO, it is necessary to continue to give NOP to SDI.
    Since the AD conversion data is output later than the command, the same cycle that data after NOP comes out
    If register read commands are overlapped, SDO in that cycle is not output.
    SDI Channel (0X0CFF) → NOP → NOP → NOP · · · NOP → Channel Read
    SDO - → - → Channel 0 data → Channel 1 data · · · Channel 6 data → ❛ L fixed

     

     

    Best Regards

    HOD

  • 0
    •  Analog Employees 
    on Feb 8, 2018 11:46 PM

    Hi HOD,

       It is recommended to perform reset on the AD7091r-8 after power up. This will place the part in default including the registers. In reading or writing to the AD7091r-8 register, CS must be low. When trying to read a register there is delay, like when you write to register to read a specific register, the result will be on the next CS falling edge. You can refer to the figure 52 of the datasheet for the timing diagram when reading register.

       There is something I need to confirm on your 3rd question, I will get back to you.

    Regards,

    Jonathan

  • 0
    •  Analog Employees 
    on Feb 13, 2018 12:18 AM

    Hi HOD,

       For the 3rd question. After writing to the channel register, the AD7091 starts conversion and the SDO outputs the conversion result but this is in a one latency cycle. Please clarify an overlapped in read command. Does it mean a read command for a 4 channel then while reading a write to register happen for another read command?

    Regards,

    Jonathan