Hi All,
I have some questions about AD7466. Please take a look at the attachment.
In my PCB, the VIN voltage drops in synchronism with the CS and the third SCLK falling edge every time.
The analog and digital sections are separated on the board and the AGND and the DGND are joined at only one place
by following to the layout introduction in the AD7466 data sheet. I also checked that the Vdd is stable when VIN voltage drops.
- What do you think the cause of this voltage drops?
- Does AD7466 draw current when the CS and the third SCLK falling edge? (and that causes this issue?)
- These voltage drops have a bad influence on digital output data? (If no impact on AD conversion results, I will not
change the circuit)
Regards,
Kazu
