AD7466 VIN drops issue

Hi Kazu,

   The AD7466 is designed to provide flexible power management. At CS rising edge or at the end of each conversion, the AD7466 automatically enter power down. At power down mode the analog circuitry is powered down.

   On the next cycle, the falling edge of CS, the part begins to power up, conversion is also initiated at this point. On the third SCLK falling edge after the CS falling edge, the AD7466 will be fully powered up at this point. At this point it requires high current until it settles. At faster SCLK it will have faster conversion time and part dissipates power for a short period.

Regards,

Jonathan

Hi Jonathan,

Thank you for supporting this case. From your comment, the VIN voltage drops are not abnormal but normal and possible to occur. I want to ask you two questions.

- Do you think both voltage drops at CS and SCLK falling edge could have a bad influence on digital output data?

- If the answer to the above question is yes, how I can reduce these drops? Changing LTC2055/Opamp is effective?

Regards,

Kazu

Hi Kazu,

   In addition above. At the start of every conversion or when CS goes low, the AD7466 switches from hold mode into track mode, which happened on your graph. At this time the converter is connected in the Vin input. On the third SCLK falling edge, it switch back into hold mode. The converter will start conversion, internally  it is not connected in the Vin input.

    Would you be able to change the buffer? There are recommended buffer in the datasheet which were proven to be good performance when paired with AD7466. In your questions about the effect on the digital output, I need to dig some details about it.

Regards,

Jonathan

Hi Jonathan,

The recommended buffers in the datasheet are AD8510 and AD8610 but I would like to use AD8512 or AD8620 since these parts are pin-to-pin compatible with LTC2055CMS8.

Regarding the effect on the digital output, I'm waititng for your comment.

Regards,

Kazu

Hi Jonathan,

The AD8512 and the AD8620 are not pin-to-pin compatible with LTC2055 so I would not like to use them.

I'll try to test with AD823A.

Regards,

Kazu

Hi Kazu,

   I would also recommend putting a cap on the front-end of Vin. The glitch during transition from hold to track to hold is expected during these transition but need to minimize and settled and putting a cap and a front end amplifier driver is essential, especially on the hold to track transition as on the track mode, the sampling cap will be charge with the voltage level that needs to be sampled by the ADC. The second glitch after 3 SCLK falling edges, this is the transition from track to hold mode. The glitch that was measured is on the Vin side, at this point the Vin is disconnected from the ADC core or sampling cap, the charge or voltage level in the sampling cap will be the one that will be converted by the ADC. During track mode it is important that the voltage is settled, around 0.5 lsb to prevent error, before it goes to hold mode since this is the voltage that charge the sampling cap.  The article on this link has a good explanation about what is happening during these transition of the conversion process of the ADC and it also point out how to choose the ADC Vin RC filter and ADC front end amplifier.

   To answer your question,

http://www.analog.com/en/analog-dialogue/articles/front-end-amp-and-rc-filter-design.html 

Regards,

Jonathan

Hi Jonathan,

I’ve been trying to design a RC filter following the explanation you recommended me.

http://www.analog.com/en/analog-dialogue/articles/front-end-amp-and-rc-filter-design.html 

In the process, I’d like to confirm you with the acquisition time and the conversion time of the AD7466.

Please take a look at the attachment. Is my understanding correct?

( I use a 250kHz clock to SCLK so the tACQ and tCONV are 8.055us and 55.945us each. Am I correct?)

Regards,

Kazu