AD7466 VIN drops issue

Hi All,

 

I have some questions about AD7466. Please take a look at the attachment.

In my PCB, the VIN voltage drops in synchronism with the CS and the third SCLK falling edge every time.

The analog and digital sections are separated on the board and the AGND and the DGND are joined at only one place

by following to the layout introduction in the AD7466 data sheet. I also checked that the Vdd is stable when VIN voltage drops.

- What do you think the cause of this voltage drops?

- Does AD7466 draw current when the CS and the third SCLK falling edge? (and that causes this issue?)

- These voltage drops have a bad influence on digital output data? (If no impact on AD conversion results, I will not

  change the circuit)

 

Regards,

Kazu

AD7466VINvoltagedrops.pdf
  • Hi Kazu,

       The AD7466 is designed to provide flexible power management. At CS rising edge or at the end of each conversion, the AD7466 automatically enter power down. At power down mode the analog circuitry is powered down.

       On the next cycle, the falling edge of CS, the part begins to power up, conversion is also initiated at this point. On the third SCLK falling edge after the CS falling edge, the AD7466 will be fully powered up at this point. At this point it requires high current until it settles. At faster SCLK it will have faster conversion time and part dissipates power for a short period.

    Regards,

    Jonathan

  • Hi Jonathan,

    Thank you for supporting this case. From your comment, the VIN voltage drops are not abnormal but normal and possible to occur. I want to ask you two questions.

    - Do you think both voltage drops at CS and SCLK falling edge could have a bad influence on digital output data?

    - If the answer to the above question is yes, how I can reduce these drops? Changing LTC2055/Opamp is effective?

    Regards,

    Kazu

  • Hi Kazu,

       In addition above. At the start of every conversion or when CS goes low, the AD7466 switches from hold mode into track mode, which happened on your graph. At this time the converter is connected in the Vin input. On the third SCLK falling edge, it switch back into hold mode. The converter will start conversion, internally  it is not connected in the Vin input.

        Would you be able to change the buffer? There are recommended buffer in the datasheet which were proven to be good performance when paired with AD7466. In your questions about the effect on the digital output, I need to dig some details about it.

    Regards,

    Jonathan

  • Hi Jonathan,

    The recommended buffers in the datasheet are AD8510 and AD8610 but I would like to use AD8512 or AD8620 since these parts are pin-to-pin compatible with LTC2055CMS8.

    Regarding the effect on the digital output, I'm waititng for your comment.

    Regards,

    Kazu

  • Hi Jonathan,

    The AD8512 and the AD8620 are not pin-to-pin compatible with LTC2055 so I would not like to use them.

    I'll try to test with AD823A.

    Regards,

    Kazu