Post Go back to editing

AD7328 cpol and cpha spi ?

Sir, how are you ?

About the AD7328, where the DOUT frames ? Wich values to CPOL and CPHA ?

Dropbox - ad7328.png 

Thank you so much!

Miguel

Parents
  • Hi Miguel,

      The AD7328 clocks out the data on the SCLK falling edge. We want to make sure that the data has settled before the microcontroller reads it. After the data clocks out on the SCLK falling edge the next rising edge the microcontroller must sample. On your attached file, the SPI mode that sample on the rising edge are 0 and 3 but mode 3 is fitting.

    Regards,

    Jonathan

Reply
  • Hi Miguel,

      The AD7328 clocks out the data on the SCLK falling edge. We want to make sure that the data has settled before the microcontroller reads it. After the data clocks out on the SCLK falling edge the next rising edge the microcontroller must sample. On your attached file, the SPI mode that sample on the rising edge are 0 and 3 but mode 3 is fitting.

    Regards,

    Jonathan

Children
No Data