AD7934 Intermittent BUSY signal

Hi there,

I'm having some issues reading from the AD7934. I will firstly describe my configuration, and then state the issue.

I have the ADC on a custom PCB, talking to an FPGA board over some trailing wires, not great for noise, but it mostly seems okay.

My ADC is configured W/B mode set to Word.

Post control register configuration, I set CS and RD low permanently so the output data bits are always driven with the latest data.

I have CLKIN free running. My CONVST falls on the first rising edge to kick off the conversion, the busy signal is detected to rise on the first (next) falling edge.

This is where I start to have a series of intermittent and linked issues. The busy signal should fall on the 14th falling edge of CLKIN. It normally does and a new reading is detected, however sometimes one of two things happen. Firstly the busy signal will fall on the 13th rising edge, not the 14th falling edge. Secondly, the busy signal will fall on the 13th rising edge and then rise again on the 14th falling edge. It will stay risen until the CONVST signal goes high again to end the conversion. I'm not sure what would happen if I delay the rising edge of the CONVST signal. When the busy signal is in the incorrect place, no new conversion is observed on the data bits.

I am not sure if this is due to some timing issue, if I'm not complying with figure 34 in the datasheet somehow. Could it be a noise or manufacturing issue on the PCB as it is intermittent?

Linked are some screenshots from my oscilloscope, The green trace is CONVST, yellow is BUSY, and red is CLKIN

A normal conversion, with busy signal rising on 14th falling edge of CLKIN. A new reading is achieved.

The busy signal falls on the 13th rising edge of CLKIN, and then rises again on the next falling edge. No new reading is achieved.

The busy signal falls on the 13th rising edge, but does not rise again. No new reading is achieved.

Any ideas?

By the way, I only have access to a terrible analogue scope for the next week, so if you want any new traces, they won't be so pretty.

EDIT. I appreciate that in the example in the pictures, the CLKIN signal is <700kHz, which is too low according to the datasheet, but this still happens if I put the frequency up.

  • 0
    •  Analog Employees 
    on Feb 7, 2018 11:22 PM

    Hi Calloutman,

       I cannot see the latest snapshot that you posted. Can re-send again please.  By the way what power mode are you using?  and what is the Vdrive supply? If it is okay, kindly share the schematic of the application.

    Regards,

    Jonathan

  • So this hasn't fixed my problem. I have changed the CLKIN signal from free running to only run while CONVST is low, with a couple of microseconds delay between the falling edge of CONVST and the first falling edge of CLKIN.

    I now have an un-shielded wire connected to my CONVST line, in series with the oscilloscope probe. When I touch the unshielded wire, the rate of errors rises substantially. As before.

    See photos.

    All photos show 10uS per division.

    Here CONVST is the top trace, and CLKIN is the bottom. CONVST goes low, and shortly after, CLKIN also goes low.

    Top trace is CLKIN, bottom trace is BUSY. The busy signal rises on the first falling edge of CLKIN, but falls on the 13th rising edge as before. BUSY goes high again on the 14th falling edge and falls when CONVST goes high again.

    A third picture where it's a bit easier to compare the two traces, again, top is CLKIN, bottom is BUSY.

  • The last snapshot I posted was the following:

    --------------------------------------------------------

    My control setup bits are the following -

    AD7934_setupBits = 12'b001101000111; // = DB11 -- DB0

    So power mode is DB11-10 which is set to 00 =  normal mode.

    I double checked that during the write phase, the setup bits were transmitted properly while CS and WR were low, and RD high.

    Schematic - 

    Vcc_ANA is 5V, Vcc_3_3 is 3.3V.

    Vcc_ANA (5V) is decoupled with a 10uF tantalum cap - TAJP106K006RNJ, (C23) and a 100nF ceramic (C24).

    C25 is a 470nF ceramic.

    C26/C27 are 10uF and 100nF.

     

    3.3V supply.

  • I have a couple of bits of information that might be important.

    Firstly, I've just noticed that when the dodgy BUSY signal is detected, the data bytes always go low (at least DB0 does) I need to double check that this happens to all the data bits, not just DB0, but I don't see why it would only just be the DB0.

    Secondly, often these errors usually come in chains, there will be a bunch of consecutive errors, and then a bunch of consecutive successful BUSY signals.  

    I will attempt to resolder the AD7934 tomorrow, just in case there is some dodgy solder connection causing this somehow. I could also replace it with an AD7933 if that would be helpful?

    EDIT. finalfthing I forgot to mention, my CS, WR, and WB pins are driven by open collector outputs on my fpga with 1k pull up resistors. This means the low to high transition time on these lines is a little slow. 

  • I am still having trouble with this. I've a few more interesting clues, but no solution.

    I have re-soldered the IC with an AD7933, replacing an AD7934, which hasn't made a difference.

    I have added extra decoupling caps to the 3.3V logic supply which hasn't helped.

    I have noticed two other things that might or might not be of concern.

    My CS and WR signals have a rather slow rising edge (200ns), as they are generated from a 1k pull up/open collector circuit. Could this cause a problem?

    I've noticed that if I redo the write to the control register, the problem sometimes will sometimes go away. That is until I do another write to the control register and it comes back.

    Could ringing on the CONVST line cause issues? The pulse edges have quite a bit of ringing on them at the moment.

    I'm getting quite frustrated. Any further ideas to try?