From the datasheet I see SDI Tsu = 12ns and Th = 10ns, this leaves only 3ns from the 25ns SCO clock cycle! How is it possible to design a circuit to meet these worst case numbers?
AD7763
Production
The AD7763 high performance, 24-bit, S-? analog-to-digital
converter (ADC) combines wide input bandwidth and high speed with the benefits of S-? conversion...
Datasheet
AD7763 on Analog.com
From the datasheet I see SDI Tsu = 12ns and Th = 10ns, this leaves only 3ns from the 25ns SCO clock cycle! How is it possible to design a circuit to meet these worst case numbers?