From the datasheet I see SDI Tsu = 12ns and Th = 10ns, this leaves only 3ns from the 25ns SCO clock cycle! How is it possible to design a circuit to meet these worst case numbers?
From the datasheet I see SDI Tsu = 12ns and Th = 10ns, this leaves only 3ns from the 25ns SCO clock cycle! How is it possible to design a circuit to meet these worst case numbers?