From the datasheet I see SDI Tsu = 12ns and Th = 10ns, this leaves only 3ns from the 25ns SCO clock cycle! How is it possible to design a circuit to meet these worst case numbers?
The minimum set up and hold time spec of the AD7763 which 12ns and 10ns respectively do not mean they add together. The minimum spec means that these are the minimum values to ensure the AD7763 correct write to register. For example, a set up time of 12ns(min spec) would mean that the hold time can be 13ns for a max SCO=40Mhz.