AD4002 SDO contention

Hello,

I'm trying with AD4002 for 18-bit application, one feature mentioned in datasheet looks confusing to me:

"If multiple AD4002/AD4006/AD4010 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up."

does that mean the SDO is open-drain based, given pull-up resistor available for busy mode? How to detect such contention and correct those corrupted bits or even meta-stable ones? i.e., how should we use this feature, or rather be avoided anyway?

thanks,

David

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  • 0
    •  Analog Employees 
    on Mar 8, 2018 5:13 PM

    Hi David,

    That's correct that the SDO pin is open-drain based and it requires a 1k pull-up resistor tied to VIO as shown in the datasheet, so all parts connected to FFPGA or any other digital host should have the SDO pins as logic high(1). One of the way that I can think of to detect the contention is that if one of the parts has its SDO pulled to logic low(0),i.e. a sign of contention. Note that there is plot in the datasheet(figure30) that shows the tDSDO vs load capacitance, where load capacitance would increase with multiple parts and may affect the full throughput.

    regards,

    LLoben

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  • 0
    •  Analog Employees 
    on Mar 8, 2018 5:13 PM

    Hi David,

    That's correct that the SDO pin is open-drain based and it requires a 1k pull-up resistor tied to VIO as shown in the datasheet, so all parts connected to FFPGA or any other digital host should have the SDO pins as logic high(1). One of the way that I can think of to detect the contention is that if one of the parts has its SDO pulled to logic low(0),i.e. a sign of contention. Note that there is plot in the datasheet(figure30) that shows the tDSDO vs load capacitance, where load capacitance would increase with multiple parts and may affect the full throughput.

    regards,

    LLoben

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