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AD4002 Recommended for New Designs
The AD4002/AD4006/AD4010 are high accuracy, high speed, low power, 18-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital...
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AD4002 on Analog.com

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AD4002 SDO contention



		

			

									
					    DavidChen
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Mar 2, 2018 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hello,
    
 
    I'm trying with AD4002 for 18-bit application, one feature mentioned in datasheet looks confusing to me:
    
 
    "If multiple AD4002/AD4006/AD4010 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up."
    
 
    does that mean the SDO is open-drain based, given pull-up resistor available for busy mode? How to detect such contention and correct those corrupted bits or even meta-stable ones? i.e., how should we use this feature, or rather be avoided anyway?
    
 
    thanks,
    
 
    David
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 Single Channel A/D Converters
                
                                                    
                 ad4002
                
                                                    
                 Precision A/D Converters
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Mar 8, 2018 12:13 PM
            
            
					
      
	
      

		
		
      
					
      Hi David,
      
 
      That's correct that the SDO pin is open-drain based and it requires a 1k pull-up resistor tied to VIO as shown in the datasheet, so all parts connected to FFPGA or any other digital host should have the SDO pins as logic high(1). One of the way that I can think of to detect the contention is that if one of the parts has its SDO pulled to logic low(0),i.e. a sign of contention. Note that there is plot in the datasheet(figure30) that shows the tDSDO vs load capacitance, where load capacitance would increase with multiple parts and may affect the full throughput.
      
 
      regards,
      
 
      LLoben
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Aug 2, 2018 12:02 PM
            
            
					
      
	
      

		
		
      
					
      This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

      Thank you,
      EZ Admin
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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