Problems with conversion time of AD7124-4

Hi, Jay.

I'm confused with your Filter settings. On the above statement you have mentioned that you set FS=4, SINC4 filter? You have mentioned that it gives you 1ms conversion time. But on the program flow, you have set filter with SPS=25, FS = 4 at full power mode. This will not probably give you a 1ms conversion time. Can you clarify your actual ODR, Filter register settings and power mode? In continuous conversion mode when single channel is enabled, the first conversion in the sequence requires a settling time and the succeeding conversion occurs at the selected ODR. The settling time will depends on the filter settings. In single conversion mode, the part is placed in standby mode after the conversion is complete. The timing for the very first conversion will take longer than a standard continuous conversion mode because it needs approximately 130 MCLK cycles or about 211.59us extra time (full power mode) to power up and settle before the conversion begins.

Thanks,

Jellenie

Hi, Jay.

Can you try to switch to continuous conversion mode and monitor your DRDY pin if it is pulsing at correct output data rate of 208.2us? This is just to check if the ADC is converting at the correct ODR.

Thanks,

Jellenie 

Hi Jellenie,

Thanks for your reply. Sorry for the confusion. The post filter bits (19:17) are set to 000. FS = 4,  power mode = full. (For some reason I'm not able to edit the original post)

Calculating settling time, 

T = (4 *32 * 4 + 95)/614.4 *10 ^3 

~= 1 ms.

Even accounting for the extra 211.59uS, a delay of 2ms in lines 7 and 14 should yield the correct result, right? But I'm not seeing that. Only providing a delay greater than or equal to  8ms tend to yield the right result. Why is that so?

If you feel my register settings are wrong, please help me with the right configuration to get a settling time of 1ms for every conversion in single conversion mode.

Thank you

Hi, Jay.

In continuous conversion mode, when you have selected a single channel, the very first conversion in the sequence requires a settling time and the succeeding conversion occurs at the selected ODR. When you enabled multiple channels, the very first conversion requires the settling time and the succeeding conversions will require a slightly shorter time than the settling time. The timing for the very first conversion in single conversion mode will take longer than a standard continuous conversion mode because it needs approximately 130 MCLK cycles or about 211.59us extra time (full power mode) to power up and settle before the conversion begins. With FS=4 , SINC4, Full power mode, single channel enabled, Tsettle at the very first conversion is 988uS while the throughput time for succeeding conversions is 208.3uS (4.8ksps). You can easily view this timing diagram on our Virtual Eval | Analog Devices Tool. The timing diagram on the software does not support single conversion mode so what it usually shown is the timing for continuous conversion mode.

Do you mean whatever Filter settings and power mode settings you made from the ADC, the DRDY pin is not pulsing at the selected ODR and always at default? Can you send me the register contents that you have write and read?

Thanks,

Jellenie  

Hi Jellenie,

I'm not sure how you got 208.2uS ? Could you please clarify? I thought the first conversion would be 1ms+211uS and all subsequent conversions at 1ms delay when operated in continuous conversion.

Also while looking at the DRDY pin, it was pulsing at 160mS. I had configured the ADC for continuous conversion after a reset of the ADC with a filter setting of FS = 4, Post filter = 0, SINC4, Full power mode, before looking at the DRDY pin. This pulsing frequency appears to be the default ODR I guess. I tried reading back the register as well to make sure the right values were getting written. Why is this happening?

Hi Jellenie,

I think I have resolved the issue. Turns out there was something funky happening with the filter0 register. When writing 3 bytes to it (even the default reg value) resulted in ADC reading 0 value in the data register. I also read back the filter0 value and verified if the SPI write happened correctly. But when I was writing just 2 bytes(despite the fact that filter0 is a 3 byte register), the ADC was generating the expected results. But all these issues vanished when I started using the filter1 register with setup1.

But I have a new issue at hand, which I was hoping to get your thoughts on.

For some reason during line 6 & 13, when I write to ADC_CONTROL, the excitation current gets switched off. Following is the waveform of voltage v2-v1 when line 6 and 13 is commented out.

You can see the 3 ms negative pulse and 3ms positive pulse as expected. But when line 6 and 13 is not commented out, this is v2-v1,

You can see at the end of 1ms the voltage becomes zero for 2ms. This is the delay I have setup after I write to ADC_CTRL and initiate the conversion. It looks like the excitation current went to zero.

Do you know what might be happening?

Thank you

Hi, Jay.

The excitation currents are disabled in standby mode. So this could be the time when the excitation is switched off after performing a single conversion plus the settling time of the excitation current upon exiting standby mode.

Thanks,

Jellenie 

Hi, Jay.

Yes, I think you have a point there. On the first figure, it is 3ms but you have mentioned that it is expected. I think it should also be pulsing at 2ms? Is that correct? Looks like there's an extra 1ms. Can you check the flow of your code? Can you try to run the first cycle only and comment out 10?  

Thanks,

Jellenie

Hi Jellenie,

But it looks like the excitation current is switched off as soon as I write to the ADC_CONTROL register to initiate a conversion. From the scope, it's clear the current stays on for the 1ms in line 5. Shouldn't the current stay on for the duration of the conversion(in addition to the delay in line 5) and turn off when the conversion is over and the ADC is in standby mode? For my filter register setting that is approximately 1ms. In that case, the plot should have the pulses at +/- 0.4 for about 2ms instead of 1ms?

Best,

Jay

Hi Jellenie,

The 3ms is what is expected because of the delays total 3ms and that is the duration for which the excitation current is on.

I think I have figured out why the pulse is on for only 1ms. I write to the IO_CTRL1 to activate the excitation current, a ms before the negative pulse but since the ADC being in standby mode it doesn't switch on the current and hence we see 0v for 1ms. Then as soon as I write to the ADC_CTRL register the ADC is out of the standby mode and it switches on the excitation current. The current stays on for 1ms which is the duration of the settling time and then turns off when the conversion is over and the ADC goes into standby mode.

I think I will be able to resolve my issues if there was some way to not let the ADC go to standby mode after performing a conversion in the single conversion mode or if the excitation current is not disabled as it enters the standby mode. Is that possible?

Thank you,

Jay