AD7124-4 PGA Input-Voltage Requirements


I'm working on an RTD measurement design and comparing the specifications of AD7124-4 from ADI and ADS124S06 from TI.

In ADS124S06's datasheet, there are equations for PGA input/output range (refer to the following figure). According to these equations, user should design the input common-mode voltage near half the supply voltage to maximize the usable output voltage range.

In AD7124-4's datasheet, however, I don't see any description about this issue. Is there any limitation about input common-mode voltage for AD7124-4 other than "Absolute AIN Voltage Limits"?

What architecture of the PGA does AD7124-4 use?