Varying conversion rate for AD7626

We are designing an acquisition system in which the sampling rate must be continuously variable, say between 2 and 5 MHz. The AD7626 is one of the devices we are looking that. Are there any restrictions as to how freely one may initiate the conversion through its CNV signal? Can the sampling rate perhaps only change at a specific fraction between conversions?

Are there perhaps pitfalls when it comes to the clocking of the data? Is the echoed or the self clocked mode to prefer if the sampling rate has to change?

Best regards



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[edited by: @skowalik at 12:04 PM (GMT 0) on 17 Jun 2020]
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    •  Analog Employees 
    on Jun 17, 2020 12:03 PM 5 months ago

    AppNielsen101,

    It should be possible to do what you would like as long as you ensure you have completed the previous conversion and read out the data before issuing the next conversion start.  There are likely to be challenges with your approach as the input signal conditioning for your application will have to be designed to support the full range of nyquist bandwidths (1 to 2.5 MHz), including designing appropriate anti-alias filtering.   Then there will be the problem of analyzing the data once you've captured it;  how will you keep samples and sample rate information correlated?

    With regards to the interface I would recommend using the echoed clock mode as there are advantages in the more compact payload  (no header) which could be advantageous in terms of simplifying your controller design.

    Hope that helps

    Sean 

  • Hi Sean, thanks for the answer, which is encouraging. The anti-alias filter will be fixed, and based on the lowest samling rate. The sampling rate control and the processing of samles will be done by the one and same FPGA, so there will be short burst of data with a fixed rate, and then the system may move to another rate. This should allow us to correlate samples and the sample rate.

    The AD7626 seems like a fine candidate for such a job, and we will continue the design process. However, should you think of an alternative A/D-converter of comparable resolution and speed which would support a varying conversion rate, just let us know. We realize that a varying conversion rate is quite in opposition to the design criteria of most A/D-converters, and having an alternative may eventually save us.

    Best regards

    Ole 

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  • Hi Sean, thanks for the answer, which is encouraging. The anti-alias filter will be fixed, and based on the lowest samling rate. The sampling rate control and the processing of samles will be done by the one and same FPGA, so there will be short burst of data with a fixed rate, and then the system may move to another rate. This should allow us to correlate samples and the sample rate.

    The AD7626 seems like a fine candidate for such a job, and we will continue the design process. However, should you think of an alternative A/D-converter of comparable resolution and speed which would support a varying conversion rate, just let us know. We realize that a varying conversion rate is quite in opposition to the design criteria of most A/D-converters, and having an alternative may eventually save us.

    Best regards

    Ole 

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