AD 7172-4 sampling rate not updating

Hi,

Can you provide more details about the register map settings? Have you tried to confirm the filter register by reading back the register value? Did you read the correct value?

If you can monitor the DRDY upon power with /CS low and check if it is pulsing at default ODR. Then try to change the filter register, read back the same register to confirm value then monitor again the DRDY pin. Can you check this please and share the digital scope shot?

Thanks,

Jellenie

Hello,

I tried reading back the register  value and it is correct  and also monitored DRDY pin with CS low , it is pulsing properly till 1007 S/S rate , but after that the sampling rate doesn't match the set filter value . 

The register map settings are :-

Using single ended mode.

1. Interface mode register : ( 0x0041 ) data stat enabled

2. channel 0 register : ( 0x8064 )       AIN3 as +ve  i/p   and  AIN4 as -ve  i/p  (gnd).

3. Setup config 0 : ( 0x0010 ) External reference AIN0 and AIN1

4.Filter config 0 :  0x0000 

5.ADC Mode register : ( 0x0000 )  continous conversion mode.

Thank you,

Faiz.

Hi.

Do you have exactly an example scope shot of your digital interface for example for a certain filter register settings (set ODR), how the DRDY is pulsing? If it is not pulsing at correct ODR, can you tell what ODR does it corresponds to? 

What do you mean as well by 1007s/s rate? Is it for the default ODR of 31.25ksps? So you are monitoring the DRDY pin with 31.25ksps and it looks okay until the 1007 samples (conversions)? Is there any changes with setup when it happens, and again what ODR does it corresponds until that case?

I would suggest if you can put in a table what's happening on your test setup it might be easy for us to understand. So for example. Put in a table the data you write to the filter register, the corresponding data you read back on the same register to confirm that they correct, then the corresponding ODR that you see in scope shot, etc.

Thanks,

Jellenie

Hi.

Do you have exactly an example scope shot of your digital interface for example for a certain filter register settings (set ODR), how the DRDY is pulsing? If it is not pulsing at correct ODR, can you tell what ODR does it corresponds to? 

What do you mean as well by 1007s/s rate? Is it for the default ODR of 31.25ksps? So you are monitoring the DRDY pin with 31.25ksps and it looks okay until the 1007 samples (conversions)? Is there any changes with setup when it happens, and again what ODR does it corresponds until that case?

I would suggest if you can put in a table what's happening on your test setup it might be easy for us to understand. So for example. Put in a table the data you write to the filter register, the corresponding data you read back on the same register to confirm that they correct, then the corresponding ODR that you see in scope shot, etc.

Thanks,

Jellenie

Hi,

when i set the ODR to 2sps , 100sps, or any other ODR till 1007sps the DRDY pin is pulsing at the correct ODR but when the ODR is changed further after 1007sps, like 5208sps or further then the DRDY pin is not pulsing at the correct ODR , Like if i set ODR to 5208sps the DRDY pin is pulsing at 3.12 KHZ .

The table and scopeshots are attached

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/425/IMG_5F00_20200608_5F00_124520.jpg

 /resized-image/__size/320x240/__key/communityserver-discussions-components-files/425/6862.IMG_5F00_20200608_5F00_124955.jpg

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/425/IMG_5F00_20200608_5F00_124641.jpg

/resized-image/__size/320x240/__key/communityserver-discussions-components-files/425/Screenshot-_2800_183_2900_.png

Regards

Faiz.

Hi,

What you are seeing is actually normal or correct. By default the single cycle (SING_CYC bit) setting is enabled. This mode allows the output data rate to be equal to the settling time, this is useful if you want to output your data at the same time.  

Sinc5+Sinc1 filter achieves single cycle setting automatically at output data rates of 2.6ksps and less. Thus you will noticed that the data rate below 2.6ksps or what you mentioned 1007sps doesn't affect by the SING_CYC bit. When multiple channels are enabled, the ADC also automatically in Single cycle setting. Because settling time is needed when the channel is changed.

You can easily view or understand how the timing works using our Virtual Eval Tool. Please see link and play around with it.

Thanks,

Jellenie