AD7780 BPDSW Pin

Hello

I'm not sure if I got function of PDSW right. In datasheet and reference designe the IN- of Load cell is connected to PDSW.

In the schematic of EVAL Board this isn't the case. What is the advantage if I connect the IN- Pin to PDSW?

If I connect the IN-  pin to PDSW I don't have to put it on GND and can switch it of?

Best regards



I completed my text
[edited by: Fabi5 at 7:56 PM (GMT 0) on 22 May 2020]
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  • +1
    •  Analog Employees 
    on May 23, 2020 6:04 AM

    Hi,

    The bridge power down switch (BPDSW) are used for transducer such as load cells that could turn off the load cell while not converting, ensuring the absolute minimal power consumption of the system. The switch is connected in series between the negative of the load cell to GND.

    The /PDRST controls the switch, so you have to change the status of this every time you want to open or close this switch. When PDRST is high, the bridge power-down switch is closed. When PDRST is low, the switch is opened. I would suggest to close the power switch prior to taking the device out of standby. This allows time for the sensor to power up and settle before the ADC powers up and begins sampling the analog input.

    If BPDSW is unused you can just leave it floating but please ensure that the switch is off.

    Thanks,

    Jellenie

  • What is actual the maximum voltage I can amplify? I think of the maximum input range which can be amplified.

    * Is it 100mV at Gain 1 

    *1.1 V at Gain = 128, FILTER = 1, AVDD ≤ 3.6 V ?

    from page three of the datasheet?

    Best regards

  • 0
    •  Analog Employees 
    on May 26, 2020 7:34 AM in reply to Fabi5

    Hi, 

    The differential input voltage range (AIN+ - AIN-) is from +/-VREF/GAIN. So if you have AVDD=3.6V and VREF=3.6V then you can have a differential input voltage of +/-3.6V at Gain=1 and +/-28.125mV at Gain=128. However, the absolute AIN voltage limits at each pin is dependent on Filter and gain mode. So at Gain=1 the voltage at each AIN pins (AIN+ or AIN-) needs a 100mV headroom from the supply rails. With Gain=128 and FILTER=1, AVDD ≤ 3.6 V, a 1.1V headroom is required at each AIN pins.

    This means the absolute voltage on either analog input pin should not exceed 100mV to 3.5V at Gain=1, 1.1V to 2.5V at Gain=128, Filter=1, AVDD≤ 3.6 V and the difference between the two input pins that can be converted is +/-3.6V/Gain.

    Thanks,

    Jellenie

     

Reply
  • 0
    •  Analog Employees 
    on May 26, 2020 7:34 AM in reply to Fabi5

    Hi, 

    The differential input voltage range (AIN+ - AIN-) is from +/-VREF/GAIN. So if you have AVDD=3.6V and VREF=3.6V then you can have a differential input voltage of +/-3.6V at Gain=1 and +/-28.125mV at Gain=128. However, the absolute AIN voltage limits at each pin is dependent on Filter and gain mode. So at Gain=1 the voltage at each AIN pins (AIN+ or AIN-) needs a 100mV headroom from the supply rails. With Gain=128 and FILTER=1, AVDD ≤ 3.6 V, a 1.1V headroom is required at each AIN pins.

    This means the absolute voltage on either analog input pin should not exceed 100mV to 3.5V at Gain=1, 1.1V to 2.5V at Gain=128, Filter=1, AVDD≤ 3.6 V and the difference between the two input pins that can be converted is +/-3.6V/Gain.

    Thanks,

    Jellenie

     

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