Timing specification of AD2S1210

Hello

I have 2 questions.

1. Table2 of AD2S1210 datasheet shows t2 is delay CS falling edge to WR/FSYNC rising edge.

But figure31 shows t2 is delay CS falling edge to WR/FSYNC falling edge?

Is figure31 correct?

If figure31 is wrong, could you send correct figure?

2. Table2 of AD2S1210 datasheet shows t9 is delay between successive write cycles.

But figure31 shows t9 is delay WR/FSYNC rising edge to RD falling edge?

Is figure31 correct?

If figure31 is wrong, could you send correct figure?

Best regards

N.Kokubo



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[edited by: @skowalik at 1:18 PM (GMT 0) on 14 Feb 2020]
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  • +1
    •  Analog Employees 
    on Feb 14, 2020 1:15 PM

    Kokubo-san,

    1) T2

    The text in Table 2 is incorrect and should be falling edge CS to falling edge WR/FSYNC.  This can be inferred from T5.

    Again I will make this correction.

    2) T9

    The same timing is applied between successive memory accesses.  The timing is correct in the table.  I will consider revising this description to make it more clear.

    Sean

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  • +1
    •  Analog Employees 
    on Feb 14, 2020 1:15 PM

    Kokubo-san,

    1) T2

    The text in Table 2 is incorrect and should be falling edge CS to falling edge WR/FSYNC.  This can be inferred from T5.

    Again I will make this correction.

    2) T9

    The same timing is applied between successive memory accesses.  The timing is correct in the table.  I will consider revising this description to make it more clear.

    Sean

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