About AD7658 Specifications

Hi all,

 

I use the AD7658 in Serial Mode(SER/PAR^/SEL = HIGH).

There are two questions about characteristics.

 

①Timing in Serial Read Operation

 

According to Figure 32, data is valid after the falling edge of SCLK.

This is specified as the minimum of t20.

 

It is difficult to acquire data in synchronization with the clock, so please tell me the maximum value of t20.

 

②Serial interface operation

 

DataSheet (Rev. D | page 25/32) has the following description:

>> After the rising edge of CONVST x,  the BUSY signal goes high to indicate that the conversion has  started.

 

However, the conversion does not start with CONVST (LOW → HIGH),

but the conversion starts with CONVST (LOW → HIGH → LOW → HIGH).

*See attached image

 

(1)CONVST (LOW → HIGH)

 

(2)CONVST (LOW → HIGH → LOW → HIGH)

 

This occurs during the first conversion after power-up.

In subsequent conversions, The conversion starts with CONVST (LOW → HIGH).

 

Thanks

 

Takahiro

Parents
  • +1
    •  Analog Employees 
    on Feb 12, 2020 8:19 PM 9 months ago

    Takahiro,

    The data on the AD765x family is updated on the rising edge of the data clock and thus should be fully settled/valid on the falling edge of clock.  If possible you should use the falling edge of your serial data clock to read in the data to your processor.  However if this is not possible, you will then have the entirety of the clock low time plus t17 (22ns) to read out that bit before the bit is lost.  Thus the maximum time is related to your serial clock rate and the pulse widths of that clock.

    On your second point it looks like the device may be powering up in a weird state and that by you putting the part into a partial power down mode and then waking it up it begins to operate normally.  It would be beneficial to know more about your hardware setup to perhaps make further recommendations how to avoid having to enter the sequence you described.

    Regards,

    Sean

Reply
  • +1
    •  Analog Employees 
    on Feb 12, 2020 8:19 PM 9 months ago

    Takahiro,

    The data on the AD765x family is updated on the rising edge of the data clock and thus should be fully settled/valid on the falling edge of clock.  If possible you should use the falling edge of your serial data clock to read in the data to your processor.  However if this is not possible, you will then have the entirety of the clock low time plus t17 (22ns) to read out that bit before the bit is lost.  Thus the maximum time is related to your serial clock rate and the pulse widths of that clock.

    On your second point it looks like the device may be powering up in a weird state and that by you putting the part into a partial power down mode and then waking it up it begins to operate normally.  It would be beneficial to know more about your hardware setup to perhaps make further recommendations how to avoid having to enter the sequence you described.

    Regards,

    Sean

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