I'm DFAE in Japan. Our customer connect AD7091R-5, AD7415 and others with I2C interface in the system. When the system is powered off, both SCL and SDA are into LOW. His end-user suspects that there is an IC in his circuit that pulls those signals LOW. Then he wants to know the equivalent circuit for SCL and SDA in the two ICs and recognize that they are not the cause. Could you please help us ?
Can you clarify what he means by powered off? If the entire system is powered off I would expect that there would be no voltage on SDA and SCL as there would be no bias.
Recall that the I2C standard specifies that the SDA and SCL pad drivers are open collector or open drain and thus all they can do is provide a low impedance path to ground. Thus there must be something to pull the bus back up to the supply which is typically done by 2.2K resistors to the I/O supply.
What may be happening here is, assuming supply for devices powered down, that because the supply for the devices is being removed (driven to zero) the user might be forward biasing ESD diodes which are overcoming the pull-up resistors and pulling the bus low, however in this case I would think the voltage would be slightly above 0 (i.e. a diode drop).
I would review the schematic with the customer to understand what is exactly the fault condition and come back to us with the additional information. It may be that this is a power sequencing issue. However, if this is a matter of saving current then both the AD7091R-5 and AD7415 have features to allow them to be biased while consuming low power through software.
Thank you very much for your support.
I've communicated the customer. Apparently, more than two types of PCBs, including his PCB, are connected to the system. The pull-up resistor of the bus is mounted only on the end user's PCB, and when only his PCB is powered off, SCL and SCA become voltages close to 0V and I2C communication seems to stop.
The way around this is to leave the power up (if possible) and to write either stop addressing the AD7091R-5/AD7415 to talk or otherwise force those units to go into a low power state. This will prevent the loading with no need for additional components.
The customer had a conference call with his end-user. They seem to want to solve this problem somehow and have the following additional questions. Sorry for your cooperation as he needs your answer to convince the end-user.
Q1. Would be ESD diodes absolutely necessary for the SCL and SDA internal circuits? Would be there no IC with the same function without the ESD diode?
Q2. Would be there a way to switch to Hi-Z instead of LOW when the power is off? We would like to find a way not to be LOW.
See my answers below.
Hiroyuki.D said:Q1. Would be ESD diodes absolutely necessary for the SCL and SDA internal circuits? Would be there no IC with the same function without the ESD diode?
My expectation is that all semiconductor devices are going to have ESD protection to ensure the quality of their product. Thus my expectation is that NO there would NOT BE a solution available in the market without ESD Protection.
Hiroyuki.D said:Q2. Would be there a way to switch to Hi-Z instead of LOW when the power is off? We would like to find a way not to be LOW.
If power is removed from the board there is no means by which to make the existing devices Hi-Z. Any solution that would prevent the loading would require some form of power to be delivered to the board short of some sort of normally open electromechanical relay in the SDA, SCL path.
The best solution is my mind at this point is to leave the unused board powered and to update it's control software to power down the loads on the bus while it is not in use. This has the lowest risk (as there is no hardware redesign) and the shortest response time.