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AD7124 FAQ: What are the differences between the standard AD7124-4/8 and the B-grade

Question: What are the differences between the standard AD7124-4/8 and the B-grade?

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[edited by: JellenieR at 2:56 AM (GMT 0) on 4 Feb 2020]
  • Answer: There are some key differences between the B-Grade (AD7124-xBBCPZ/AD7124-xBBCPZ-RL) and the standard (AD7124-xBCPZ/AD7124-xBCPZ-RL) AD7124-4/8. Choice will depend on your application requirements, here are the key differences between the two types

    These includes:

    • Package
    • Reference TempCo Specification
    • Multichannel Measurement (channel sequencing) settling time (at Gain=1)
    • Excitation currents status/mode in standby mode
    • Gain Registers value when MCLK & SCLK are Asynchronous


    • The B-grade is available in the LFCSP package only whereas the standard is available in both TSSOP and LFCSP. The LFCSP package is 5 x 5 mm package for both B-grade and standard but the height is the key difference, where the B-grade height is 0.95 mm and the standard is 0.75mm.

    Reference TempCo:

    • The B-grade AD7124-4/8 internal reference has a tempco of 10 ppm/’C max. The internal reference on the standard silicon (LFCSP) has a temp of 15 ppm/’C max

    Multichannel settling time (at G=1):

    • The standard silicon, when used in multi-channel mode, does not settle within the allowed time when switching channels for gains of 1 when high output data rates are used in conjunction with large resistive loads. The B-grade silicon includes a pre-charge buffer which aids the settling and hence ensures that all conversions are fully settled within the allowed time.

    Excitation currents status in standby mode:

    • On the standard silicon (LFCSP and TSSOP), the excitation currents are disabled when the ADC is placed in standby mode. On the B-grade, the excitation currents can remain active in standby mode. This is useful when current consumption minimization is not important. Some customers use single conversion mode as a timing mechanism to provide conversions within timeslots. In this use case, keeping the excitation currents enabled during standby mode minimizes the power up time.

    Gain Registers value when MCLK & SCLK are Asynchronous

    • On the standard silicon, the gain register can reset to its default value periodically if SCLK and MCLK are asynchronous. So, if internal FS calibrations or system FS calibrations are performed in a system where SCLK and MCLK are asynchronous, the gain register should be read periodically to ensure that it has not reset. On the B-grade, the gain register does not reset even when SCLK and MCLK are asynchronous.