I hope that there would be helpness for me.
I am about to transfor the Resolver converter chip which is the solution of my unit to other chipset (the AD2S1210).
But I don't understand that some the function of the AD2S2110, that is as blow as,
1. I thik that there seems to be some error by delaying of EXT singal between AD2S1210 between the reslover sensor.
According to the Data sheet, for the EXT signal, recommendating buffer circuit, I quess that it makes some delay so that RD converter would get some offset error.
2. Accorcding to the data sheet, In confiugration write mode,
it is not clear that the explanning of datat sheet and the timing diagram.
-. I expect that the writing signal is one more time active after latching the address at falling edge of the WR signal.
1. For your first question I believe that you are questioning the 180 degree phase introduced by the inverting stage of the excitation buffer. You are correct that at the resolver side, if you directly connected EXC and EXCB to the resolver you would get a positional offset out of the RDC of 180 degrees. This is easily corrected by reversing the polarity of the connection at the rotor connections. Note: That miswiring of the stator wires at the COS and SIN input pairs can also cause positional offset errors.
2. For your second question in configuration mode you must address the register to be written first by writing to the part. From the datasheet we now that a logical 1 in the MSB (D7) of the parallel bus will instruct the device that the data on D[6:0] is an address and conversely if D7 is a 0 then D[6:0] is register data.
So in this sequence we see the following operations with the appropriate interface timing assigned to critical features of the operation.
A) Part is placed in configuration mode (A1, A0 = 1)
B) CS is asserted enabling the device for communication
C) The address for the register write is written to the part
D) The data for the register is written to the part (not CS did not have to change state in between however the diagram is indicating it can).
E) Following the write A1, A0 change state to go to another mode (illustrating the hold timing from data write to A1, A0 state change.
F) Followed by a reentry into configuration mode for a subsequent write operation.
I hope that answers your questions.
1. May be, there was some misunderstand for my quesion.
My first question is as blow as
2. For my second question, I understand your tip as blow as
Thank you for your helpness.
1) On your first question I understand now that you were describing the phase delta between the synthetic reference and the excitation component as observed at the component inputs. While there is a physical delay the tracking loop is able to lock to the incoming signal as long as the overall phase lead or lag is within 45 degrees. There is an option to allow the loop to attempt to lock over the full 360 range but this has its trade-offs. As the absolute angular position is relative to the modulation generated by the resolver itself there should be no error attributed to the phase delay through the excitation loop under constant velocity conditions.
2) Your understanding of the interface is correct.
I got your advice.
I will draw the circuit refering to data sheet and your tip for my new Unit.
I have a question as below as
-. There is no table about the anglar position value in the data sheet.
Is It the same as the table on the AD2S83 chipset.
The short answer is YES for 10,12,14,16 bit resolutions only.