LTC2387 Sample Clock Frequency and Layout


I am using the LTC2387-18 in an application and noticed your demo setup divides a higher frequency clock down to get 15.36 MHz. This is above the 15 MHz that the datasheet indicates as maximum. Is the 15.36 MHz fine to use? There is a much better selection of oscillators at 15.36 MHz. 

Also, due to routing constraints, I may have to distribute the LVDS CNV sampling clock through one pair of vias. I know it's generally not recommended, but not sure if it will be an issue if the vias are made as close to 50 ohm Z as possible and there are ground vias right next to them to allow for the return current to follow the layer switch. 



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