I am using the LTC2387-18 in an application and noticed your demo setup divides a higher frequency clock down to get 15.36 MHz. This is above the 15 MHz that the datasheet indicates as maximum. Is the 15.36 MHz fine to use? There is a much better selection of oscillators at 15.36 MHz.
Also, due to routing constraints, I may have to distribute the LVDS CNV sampling clock through one pair of vias. I know it's generally not recommended, but not sure if it will be an issue if the vias are made as close to 50 ohm Z as possible and there are ground vias right next to them to allow for the return current to follow the layer switch.
Which demo system are you referring to? Both the DC2290 and DC2588A use a 15MHz sample clock. While it is possible for the LTC2387 to work at a sample rate higher than 15Msps, this will reduce the already small acquisition time and is not recommended.
Regarding the vias in the CNV signal path: you will have to look at the CNV signal right at the CNV input of the ADC and make sure that it is free from ringing and that it cleanly transitions from 0 to 1 and 1 to 0.
Ah, it might be my mistake. There is a video on Arrow and Youtube featuring the LTC2387 that uses DC1216A-B and divides it by 8 with DC1075A to get 15.36 MHz. I realize now that might be Arrow's content and not an actual recommendation. I'll stick to 15 MHz just to be safe and also check the CNV signal. Thanks!
If you do not have access to a low jitter clock source, You could use the DC1216A-A 100MHz clock board and divide it by 8. This would give a sample rate of 12.5Msps.