Common mode vlotage of AD7792 AIN input

Hi

Could you helps to take a look this confusing.

This is the Analog Inputs requiremnt for AD7792.

For Absolute AIN Voltage Limits, when active or inactive the internal BUFFER and In-Amp, AD7792 have different requirement for Absolute AIN Voltage. Also, this chip have Common-Mode Voltage requiremnt.

So, my confusing is:

made a example:

1\Active the In-Amp, set Gain=4, Absolute Ain(-) =350mV, Absolute Ain(+) =400mV, whether this configuration can work well?

2\Unbuffered mode, gain=1(no in-amp), Absolute Ain(-) =0mV, Absolute Ain(+) =100mV, whether this configuration can work well?

Whether example 1 and 2 have same issues: don't match the requirement for Common-Mode Voltage.

How this 0.5V be designed, could you introduce more details about why we have to keep Common-Mode Voltage bigger than 0.5V.

BR

Parents
  • +1
    •  Analog Employees 
    on Jan 7, 2020 7:00 AM

    Hi,

    Yes, there's a restriction on the analog input range and common mode voltage when the in-amp is active to ensure that the limits are not exceeded for correct operation and to avoid linearity performance. The common mode range must be at least 0.5V when gain = 4 to 128.

    AD7792 uses an instrumentation amplifier to implement the gain stage when the gain is set between 4 and 128. For a gain of 2, the gain is implemented capacitively (the reference capacitor in the modulator is halved). An instrumentation amplifier was used for the higher gains, as it consumes less power than a capacitive PGA. The AD7790 on the other don't have an In-Amp, it only has an input buffers and the cap PGA, that's why it doesn't have the common mode requirement for gain=4 to 128.

    The analog input pins can tolerate a voltage from GND – 30 mV to AVDD + 30 mV when the gain is equal to 1 or 2 and the buffer is disabled. When the buffer is enabled, the buffer itself will require some headroom. The absolute voltage on the analog input pins must be between GND + 100 mV and AVDD – 100 mV. The buffer will be nonlinear outside this range, so the device will be unable to meet the data sheet specifications. When the in-amp is enabled (gains of 4 or higher), the in-amp itself requires some headroom. Hence, the absolute voltage on an analog input pin is now limited to GND + 300 mV and AVDD – 1.1 V. If the analog input is outside this range, the ADC will function; but the part will not meet the data sheet specifications, as the in-amp is nonlinear near the power supply rails.

    So for the above example, example 1 are not a valid inputs since it doesn't meet the minimum requirement for common mode.

    I cannot answer exactly why it is 0.5V because it's on the design process, but any real op amp have a finite voltage range of operation. Headroom limits for in-amp is more complex as the most common in-amp architectures combine two or three op amps, each with individual input and output ranges. 

    May I know what is your application and what are your input voltage requirements?

    Thanks,

    Jellenie

Reply
  • +1
    •  Analog Employees 
    on Jan 7, 2020 7:00 AM

    Hi,

    Yes, there's a restriction on the analog input range and common mode voltage when the in-amp is active to ensure that the limits are not exceeded for correct operation and to avoid linearity performance. The common mode range must be at least 0.5V when gain = 4 to 128.

    AD7792 uses an instrumentation amplifier to implement the gain stage when the gain is set between 4 and 128. For a gain of 2, the gain is implemented capacitively (the reference capacitor in the modulator is halved). An instrumentation amplifier was used for the higher gains, as it consumes less power than a capacitive PGA. The AD7790 on the other don't have an In-Amp, it only has an input buffers and the cap PGA, that's why it doesn't have the common mode requirement for gain=4 to 128.

    The analog input pins can tolerate a voltage from GND – 30 mV to AVDD + 30 mV when the gain is equal to 1 or 2 and the buffer is disabled. When the buffer is enabled, the buffer itself will require some headroom. The absolute voltage on the analog input pins must be between GND + 100 mV and AVDD – 100 mV. The buffer will be nonlinear outside this range, so the device will be unable to meet the data sheet specifications. When the in-amp is enabled (gains of 4 or higher), the in-amp itself requires some headroom. Hence, the absolute voltage on an analog input pin is now limited to GND + 300 mV and AVDD – 1.1 V. If the analog input is outside this range, the ADC will function; but the part will not meet the data sheet specifications, as the in-amp is nonlinear near the power supply rails.

    So for the above example, example 1 are not a valid inputs since it doesn't meet the minimum requirement for common mode.

    I cannot answer exactly why it is 0.5V because it's on the design process, but any real op amp have a finite voltage range of operation. Headroom limits for in-amp is more complex as the most common in-amp architectures combine two or three op amps, each with individual input and output ranges. 

    May I know what is your application and what are your input voltage requirements?

    Thanks,

    Jellenie

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