We use the AD7770 to sample 8 input channels very accurate.
We configure the AD7770 and release it to sample on 1Khz base. Also set GENERAL_USER_ CONFIG_3, Bit 4 to readback the sigma delta. We get the DRDY as expect and after each one we read the result on all channels by sending 0x8000000000000000 (read 2X32bits= 2 channels each time). This we do 4 times so we get all channels and save them. We also check if we have on bit 23 "1" for the sign number and set according ( fill vit 31 to bit 24 ="1"). All this process take 310us so we finish it before we get new sample ready. Evey 3-4 samples we get irregulare result.
If we look on the error header (we make the CRC disable) we see start from the second sample Alert bit bit 7 is on all the time, but it is very inconvenient to check what the cause of the error because the register information arrangement ( Not a specific register error for each ch).
Any clue what can cause or what test we should do to find the problem?
[edited by: Lluis at 11:43 AM (GMT 0) on 13 Nov 2019]