AD7173-8 CONTINUOUS READ MODE and Status Register

Hi

I'm DFAE in Japan. Our customer evaluate AD7173-8 on their trial board. Actually they face 2 issues as follows. Could you please help us to resolve.

Q1. In continuous read mode, since every time a different channel is read out, they want to improve it so that it reads in order from the channel with the smallest number.

Q2. The lower 4 bits of the STATUS register indicate the channel number, but Bit0 is always 1 and the channel number cannot be determined correctly.

When reading with the STATUS register alone, reading with the DATA register appended is the same. What are the possible causes?

Regards,

Hiroyuki

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  • 0
    •  Analog Employees 
    on Oct 29, 2019 3:43 PM over 1 year ago in reply to Hiroyuki.D

    Hi Hiroyuki-san,

    I apologize for the slow reply. I'll try to find the right support person for AD7173.

    Doug

  • 0
    •  Analog Employees 
    on Nov 5, 2019 8:55 AM over 1 year ago in reply to Hiroyuki.D

    Hi,

    Apologies for late response. I think this issue has been handled offline.

    Thanks,

    Jellenie

  • Dear Jellenie,

    Thank you very much for your reply. I've already resolved by Japanese ADI FAE.

    Regards,

    Hiroyuki

  • +1
    •  Analog Employees 
    on Nov 6, 2019 6:53 AM over 1 year ago in reply to Hiroyuki.D

    Hi,

    I have communicated with the ADI FAE but I will post it here as well so others from the community will be informed as well.

    Continuous conversion mode is the default power up mode. So upon power up, the ADC is continuously converting on a single enabled channel and RDY bit in the status will go low each time a conversion is complete, and when /CS is low the DRDY pin goes low.

     When you enabled multiple channels, the sequencer automatically cycles through all enabled channels in order from lowest to highest. So, for example CH0 to CH3 are enabled, when the ADC converts, the sequencer transitions from CH0 to CH1 to CH2 and then on CH3 before looping back to CH0 to repeat the sequence. The data register will be updated as soon as each conversion on each channel is available. The rate at which data is available (DRDY pulls low) for multiple channels would be dependent on the corresponding settling time for the selected output data rate (ODR) and filter type set. The user must then read the conversion result while the ADC converts the next enabled channel; otherwise, the new conversion result is lost. So it is really important to monitor the DRDY pin or the RDY bit in the status register and start reading the conversion as soon as it goes low. Enabling the DATA+STAT will tell which channel corresponds the conversions.

     In customer case, does the customer used continuous read mode? In continuous read mode, conversions are placed on the DRDY line automatically and there is no need to issue a read data register instruction. However, in continuous read mode, the data register is updated each time a conversion is read. So, if you have a slow SCLK, you may read some of the current conversion and some bits of the next conversion, leading to an overall invalid reading. In continuous read mode, you need to ensure that each conversion read is completed before the next conversion is available.

    In continuous conversion mode, ADC is continuously converting but in standby mode, most blocks are powered down. So it needs to come out of standby to power up and settle before it begins the sequence of conversions. If the customer wants to control the start of conversion, the customer can use the SYNC pin. When /SYNC is taken high the ADC begins sampling/starts conversion.

    Thanks,

    Jellenie