FPGA design files for D2390A-A evaluation board and Arrow/Terasic SoCkit Cyclone V FPGA evaluation board

I am using the DC2390A-A evaluation board for the LTC2500-32 ADC with the Arrow/Terasic SoCkit Cyclone V FPGA evaluation board.  I cannot find the design files for the Arrow/Terasic SoCkit evaluation board for use with the DC2390A-A.  I am in need of the design files to program the Cyclone V FPGA of the SoCkit evaluation board so that I can evaluate the LTC2500-32 on the DC2390A-A evaluation board.

I can't even find the pinout information for the DC2390A-A evaluation board!  So at this point, the DC2390A-A evaluation board is useless.

Thank you for any assistance with this issue!

Parents
  • Thank you for your response.  The SoCkit board file that you linked only provides the SD card image for the bootable Linux-based OS for the HPS of the Cyclone V FPGA of the SoCkit board.

    Can you also provide the files to configure the FPGA of the SoCkit for use with the DC2390A-A?

    Thanks again!

  • Yes, as per the DC2390A Demo Manual.  And all jumpers are at their default positions.

  • Attached is the full output from the "DC2390_full_datapath_test_oldclient.py" script.  As you can see, there are frequent "TIMED OUT!!" messages.

    DC2390_full_data_path_test_oldclient.py OUTPUT.txt
    Python 2.7.16 |Anaconda, Inc.| (default, Mar 14 2019, 15:42:17) [MSC v.1500 64 bit (AMD64)]
    Type "copyright", "credits" or "license" for more information.
    
    IPython 5.8.0 -- An enhanced Interactive Python.
    ?         -> Introduction and overview of IPython's features.
    %quickref -> Quick reference.
    help      -> Python's own help system.
    object?   -> Details about 'object', use 'object??' for extra details.
    
    runfile('D:/Program_Files/Analog Devices/linear_lab_tools64/python/llt/app_examples/ltc2500_family/DC2390_full_datapath_test_oldclient.py', args='192.168.1.6', wdir='D:/Program_Files/Analog Devices/linear_lab_tools64/python/llt/app_examples/ltc2500_family')
    Tuning Word:131072
    Starting client
    FPGA load type ID: 0001 - Expecting ABCD, make sure you know what you're doing!
    FPGA load revision: 0103 - Minimum is 1246, make sure you know what you're doing!
    Setting up system parameters.
    
    Okay, now lets blink some lights and run some tests!!
    Software immediate trigger...
    ready signal is 4
    After 0.0019998550415 Seconds...
    Starting address: 
    6924160
    Reading a block of less than 1M points
    Standard Deviation: 0.0
    D:/Program_Files/Analog Devices/linear_lab_tools64/python/llt/app_examples/ltc2500_family/DC2390_full_datapath_test_oldclient.py:172: RuntimeWarning: divide by zero encountered in log10
      fftdb = 20*np.log10(fftdata / 2.0**31)
    RMS voltage: 0.0
    Peak-to-Peak voltage: 0.0
    Software immediate trigger...
    ready signal is 0
    After 0.105000019073 Seconds...
    TIMED OUT!!
    Starting address: 
    7603828
    Reading a block of less than 1M points
    Software immediate trigger...
    D:/Program_Files/Analog Devices/linear_lab_tools64/python/llt/app_examples/ltc2500_family/DC2390_full_datapath_test_oldclient.py:197: RuntimeWarning: divide by zero encountered in log10
      fftdb = 20*np.log10(fftdata / 2.0**31)
    ready signal is 0
    After 0.103999853134 Seconds...
    TIMED OUT!!
    Starting address: 
    8284380
    Reading a block of less than 1M points
    Software immediate trigger...
    D:/Program_Files/Analog Devices/linear_lab_tools64/python/llt/app_examples/ltc2500_family/DC2390_full_datapath_test_oldclient.py:210: RuntimeWarning: divide by zero encountered in log10
      fftdb = 20*np.log10(fftdata / 2.0**31)
    ready signal is 0
    After 0.105000019073 Seconds...
    TIMED OUT!!
    Starting address: 
    8965876
    Reading a block of less than 1M points
    Software immediate trigger...
    ready signal is 4
    After 0.00200009346008 Seconds...
    TIMED OUT!!
    Starting address: 
    15889536
    Reading a block of less than 1M points
    Software immediate trigger...
    ready signal is 4
    After 0.0019998550415 Seconds...
    TIMED OUT!!
    Starting address: 
    22813972
    Reading a block of less than 1M points
    
    
    
    
    
    
    
    
    
    
    Writing downward ramp to LUT!
    1073741835
    Done writing to LUT! Hope it went okay!
    Test done! Enter "client.shutdown()" to shut down SoCkit board.

  • 0
    •  Analog Employees 
    on Oct 29, 2019 6:16 PM over 1 year ago in reply to HypeInst

    The output says that you have the wrong FPGA load type and load revision.

    Did you follow the attached instructions when writing the SD card?

    https://rocketboards.org/foswiki/view/Documentation/ArrowSoCKITEvaluationBoardLinuxGettingStarted

  • Yes - I precisely followed the instructions for writing the SD card and used the image that you linked (above) in your first response to my posting.

  • +1
    •  Analog Employees 
    on Oct 29, 2019 9:08 PM over 1 year ago in reply to HypeInst

    I have been informed that the DC2390 article may no longer be pointing to the most recent version of the FPGA image. Can you provide me with an email address that I can send a link to, with the most recent image. We are trying to update the article so that it points to the most recent image but I am not sure how long that will take.

Reply
  • +1
    •  Analog Employees 
    on Oct 29, 2019 9:08 PM over 1 year ago in reply to HypeInst

    I have been informed that the DC2390 article may no longer be pointing to the most recent version of the FPGA image. Can you provide me with an email address that I can send a link to, with the most recent image. We are trying to update the article so that it points to the most recent image but I am not sure how long that will take.

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