We noticed a strange data glitch on the AD4003 running the evaluation FMC card - shown below. Captured conditions were CNV rate of 1.6 MSPS and SCK rate of 80 MHz using VIO = 2.5V. We've changed the timing of our signals (CNV, SCK) and tried VIO = 3.3V.
Below is a scope capture showing the values over multiple SPI transactions where we honor the Tquiet1 and Tquiet2 thresholds. The above capture was from a Xilinx Debug ILA, which we showed was capturing the same data values as the scope when we compared them.
I've read through the datasheet a couple times and can't find another potential cause of something like this. Other ideas of what can be done? Has anyone else seen this?
Thank you for your time.
It strikes me that if the input is AC coupled that the input common mode range of the ADC might be violated. Can you please share the schematic for the front-end and what the signals…
I'm a bit confused here. I see the glitches you're referring to on the first plot but not the scope capture image. How are the results in the first plot corroborated by the scope image? Maybe I'm missing something here?
It strikes me that if the input is AC coupled that the input common mode range of the ADC might be violated. Can you please share the schematic for the front-end and what the signals at the ADC input look like. In fact I think looking at one of your later posts I think you state the input is swinging from 400mV to 1.2V which violates the input common mode range of the part. For a 5V reference you'll want to bias the inputs around 2.5V so your signal will want to swing from 2.1V to 2.9V centered on 2.5.
Sean - great catch. We have modified our design to account for our incorrect assumption about Vcom and how Vref applies to dynamic range and will take data on the design changes. We have gone back to DC coupling and adjusted the level of Vcom. Will report back on findings when we've had a chance to analyze them.
That seems to have fixed things! More testing this week, but we had some good results on Friday.