AD7998 channel-channel interference in Mode 2

I'm debugging a board which uses the AD7998 12-bit multiplexed ADC converter and appears to have channel-channel interference. There appears to be an issue with around 40% of the boards to a lesser degree.

The ADC device is used in MODE2 where 6 channels are automatically sequentially converted once the conversion registered is written to. There is crosstalk in the form of channel conversion result can be affected by the value of the previous converted channel, of course we can only see this if the previous channel is at a vastly different ( >0.5V x Vref ) potential. The worst case we have seen is 72ADU difference between the expected and actual result (biased towards the prior channel polarity) and we are frequency seeing the previous channel in the conversion sequence being affected by around 20ADU.

In the circuit there is also a AD5254 Nonvolatile Memory Digital Potentiometers to vary the gain in the signal conditioning circuit however due to the sequencing of the conversion, and that this issue is also seen in the channels not connected with the digital POT this is not thought to be the cause of the ‘crosstalk’.

Can you tell me the Track and Hold sampling time for the AD7998 operating in mode 2. Could this be an issue?

Some further information:

I2C bus at 400KHz.

Sampling sequence is channel 1 to channel 6.


The ADC is set up as follows:

configuration register: 0x03FA

The above register is set-up once only, on processor power-up.

During the conversion MUX_A0 (WRT schematic) is static.


The ADC is triggered to convert a sequence of channels 4 times in succession every 160mS.

  • 0
    •  Analog Employees 
    on Sep 12, 2019 1:51 PM over 1 year ago

    Hi RhysBR,

    Thank you for providing ample details of the issue you're facing.

    Based on the fact that the crosstalk between two channels gets worse as the voltage difference between those two channels increases, I suspect the issue is that the analog front-end circuitry driving the AD7998 inputs is not sufficiently settling the voltage kicks incurred when the AD7988's input switches open and close during the conversion and acquisition phases respectively (these switches are pictured in the Converter Operation section of the AD7998 data sheet).

    Typically we recommend putting a single-pole RC filter between the amplifier driving the ADC and the ADC inputs, as described in this article. The capacitor in that filter acts to "soften" the voltage kick by supplying some of the charge needed to charge the ADC's sampling capacitors up to the target voltage, and the filter itself has the added function of filtering out noise from those amplifiers (if necessary).

    I believe the tPOWER-UP specification is the equivalent of the acquisition time (tACQ) mentioned in the above article. That means the amount of time that the AD7998 gives the analog front-end circuitry about 1us to settle that kick. I recommend trying out 100ohm + 1800pF RC filter between the outputs of the U20/U21 amplifiers, as this filter should have both a large enough parallel capacitance to reduce the size of the voltage glitch plus a short enough time constant to settle that glitch to 12-bit accuracy in 1us.

    Let me know if you have further questions. Good luck,


  • Hi Tyler,

    Thank you very much for your quick reply and guidance. I’ll implement your suggestions to see if this resolves the issue. Hopefully this will verify the source of the problem.

    Is there any way to diminish the ‘psudo crosstalk’ effect without affecting the PCB layout?

    Could changing to a faster OPAMP help with charging the ADC’s T/H capacitor?

    Sampling is done once ( 4 samples taken and averaged ) every 160mS, the signal for each channel is considered to be in a steady state during the sampling interval. If the issue is with the buffer not responding fast enough to charge the ADC T/H circuitry, it could be easier to change the software to sample 1 channel at a time:

    Take 5 consecutive samples from 1 channel and discard the first and average the next 4 samples before moving on to perform the same on the next channel. Would this resolve the issue or just diminish the effect? Would I need to take more 'dummy' samples before the result will be stable?

    Kind regards,