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AD7709 SPI communication problem


I first read those posts :

And look after help on internet, but I found no answers.

My problem : I can't communicate properly with AD7709, I tried several codes with several SPI Mode (datasheet says Active edge is Falling edge, does active edge means edge validating datas  or edge toggling bits?) and SPI Frequency (never more than 1MHz).

I can't even read a correct answer from statut register.

My configuration: dsPIC33EP512GM706 connected to the AD7709 for RTD (3 wires config) reading.

My algorithm:


PORTEbits.RE13 = 0; //CS low
PORTEbits.RE14 = 0; //Reset
__delay_ms(1000); //Delay_s();
PORTEbits.RE14 = 1;
Write_SPI(0x22); //Low Power Mode + Filter Register
Write_SPI(0xFF); //5.35 Hz = 186.77 ms

    Write_SPI(0x01); //Write Enable + Write Operation + Power Up OSC + Configuration Register
    Write_SPI(0x09); //Config23 - 16
    Write_SPI(0x00); //Config15 - 8
    Write_SPI(0x0F); //Config7 - 0
    while(PORTEbits.RE12 == 1); // Polling on RDY pin
    Write_SPI(0x43); //Read Operation + ADC Data register
    msb = Read_SPI_AD7709(); //Read ADC Data register
    lsb = Read_SPI_AD7709();


I also tried to put delays between write & read operation. Same for Frequency clock, from 15kHz to 1 Mhz.

Can you please send me an example and/or give some advice ?

Thank you.

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  • I can't read back status, config or filter register. AD7709 is just not answering me. I can't show you DOUT, CS and RDY pin in the same chronogram, because AD7709 is already solder to my PCB and rooted to my dsPIC. I can see RDY pin toggling after a reset or after sending command 0x42 on the debugger. I'm sharing SPI bus with 2 ICs (DAC8565 & LTC2408), but I'm disabling them during test.

    It could be lovely to have those answers : 

    Which CLK edge is toggling SDI ? rising or falling? Active edge is Falling edge, does active edge means edge capturing datas or edge toggling bits?

    What Frequency clock do you advise me ? It's not clear on datasheet, we just know Max frequency (5MHz), deduced from timing figure n°2 & 3.

    Is it mandatory to put CS pin to logic high level between read & write operation ? Datasheet example says we can put SPI bus to 3 wire, so it seems to be possible but we never know.

    Does pull-up or pull-down resistance are necessary on MOSI or MISO ? 

    I'm not asking for a C code or no-OS code, but a single capture showing a write & read operation with MOSI & MISO signal could be so helpful.

    Thank you,


  • Hi,

    This means that the data is output from the ADC following the SCLK falling edge and is valid on the SCLK rising edge. As long as you are within the minimum and maximum SCLK range there should be no issue, so I think your SCLK value is valid. For CS, it is not mandatory and yes you can hardwired CS to operate in 3-wire mode. There is no need to add pull up, a weak pull-up to VDD is provided on the DIN, CS input. You can use reference drivers for other ADCs, maybe this could help. Or if you could also ask from the Microcontroller no-OS Drivers community, they might be able to help you.