AD7124-8 input circuit strong disturbance in Single Conversion Mode


I've recently encountered a strange phenomenon in Single Conversion Mode. At the beginning of the new conversion strong interference appears at both pins of the first logical channel used. The input circuit is typical - differential mode anti-alias filter 2x10k + 10nF and 2x3n3 pair to system analog GND. The interference is in the form of positive pulse of about 100mV amplitude and about 50us of time and it's present at both pins of the logical channel (because of this, differential measurement is disturbed to a less extent). The disturbance comes from the inside of the IC, it's not present anywhere beyond the input circuit. The disturbance appears only at the beginning of the first conversion after the Standby phase after previous single conversion. If the ADC is configured to take some consecutive measurements, the first one, and only the first one is disturbed, no matter what logical channel is used. The disturbance is independent of the hardware channels used, one can "move" the disturbance to any pin pair, just by reconfiguring the first logical channel used in the sequence. The distrurbance is independent of the conversion config (filter, data rate etc). Burnouts are off.

Any idea how to get rid of this? Switching to continuous conversion (or conversion in pairs - with the first conversion "lost") would be a problem.

  • 0
    •  Analog Employees 
    on Aug 13, 2019 7:00 AM over 1 year ago


    In my understanding, it is only the first channel (Channel_0) has the issue? when you tried the second channel (Channel_1) or third channel (Channel_2) in the sequence with the same analog input pins you cannot see the disturbance? Can you clarify this? When you are not taking measurements, or does not select any channel, are you still seeing this issue? If you could share the register settings and as well as your measurement setup (block diagram or schematic) it would be helpful. Do you also have a scope shots of the above scenarios so I can easily visualize the issue? Are you using the evaluation board or your own design board? Have you check the supply/reference decoupling and grounding connections? Can you also perform noise test by shorting the inputs together and bias to some voltage (usually mid supply).



  • not exactly. The issue regards to first channel used in a sequence of measurements. More exactly it regards to any physical pins connected to this channel. Any channel can be affected - e.g. I use Channel_0 in some measurements, and Channel_4 ... Channel_7 sequence in another measurements, and affected channels are Channel_0 and Channel_4. Most of the experiments I've performed using channels 4-7, but I think channel number doesn't really matters. AD7124 always selects enabled channels in order of their numbers, so always the channel with lowest number is affected, regardless of hardware pins selected.

    Example 1: chanel 4, 5, 6, 7 are enabled. Channel 4 is AIN7-AIN6, Channel 5 is AIN9-AIN8, Channel 6 is AIN11-AIN10, Channel 7 is AIN13-AIN12. Affected pins are: AIN7, AIN6.

    Example 2: chanel 4, 5, 6, 7 are enabled. Channel 4 is AIN9-AIN8, Channel 5 is AIN7-AIN6, Channel 6 is AIN11-AIN10, Channel 7 is AIN13-AIN12. Affected pins are: AIN9, AIN8.

    In fact, input circuits of AIN9-AIN8 pair is identical as AIN7-AIN6 and the disturbance is also the same. I've noticed: the higher input resistors of anti-alias filter and smaller capacitor, the higher the disturbance.

    I use my own board, but input circuits are very similar to eval board. The ADC has 0-3V3 power supply and static input voltages at mentioned inputs is 1.5V. I strongly believe, everything is OK with my board.

    I believe, the most important thing is measurement mode. I use "single sequence" mode, so after sequence of measurements ADC goes to some idle mode (automatically - I cannot prevent it, unfortunately). When new sequence starts, ADC has to exit from this idle mode and here the problem lies: the first enabled channel is selected, analog pins are connected by means of internal MUX and then something inside the ADC "powers up", creating the disturbance. The time interval from starting the measurement (CONTROL register write) to the disturbance is in the range of microseconds.

    I'll provide some scope shots soon.

  • Important note: the disturbance appears only with GAIN = 1.

    Scope shot:

    channel 2 is AIN7. Channel 3 is debug/trigger signal. The pulse is at the end of the SPI transaction writing CONTROL register. The ADC is in Idle state before the measurement.

    CONTROL register settings:


    CONFIG register settings (SETUP_4):


    (I don't remember if buffering settings are effective with Gain = 1)

    External ref is 3V, DC bias at the AIN7: 1.5V

    CHANNEL register settings (it's Channel_4 - first of enabled channels):


  • 0
    •  Analog Employees 
    on Sep 8, 2019 5:32 AM over 1 year ago in reply to MBR


    We released a B-grade of the AD7124-8 that includes a pre-charge buffer. This pre-charge buffer was added to reduce the settling time needed for the analog input to settle. ON the standard part, we have seen a settling time anomaly at high output data rates whereby the first conversion is not fully settled within the allowed time for large resistive loads. The latest datasheet discusses this anomaly. Can you order some B-grade parts and confirm whether they resolve the disturbance issue.



  • Hi,

    Not good news. The grade B version also shows similar effect, although the pulse is about 20% less of amplitude.

    Design flaw of the IC?

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  • 0
    •  Analog Employees 
    on Nov 4, 2019 10:53 AM over 1 year ago in reply to MBR


    Let me confirm this with the product owner/designer and get back to you,



  • Hello Jellenie,

    Is there any solution to this problem yet?

    We seem to suffer from almost exactly the same phenomenon, only worse since we do all the measurements in single_conversion mode or let the ADC sleep between the conversions. This means that the issue affects every single measurement and all channels regardless of the selected gain or speed. Additionally we see the disturbance pulse also after the measurement. In most cases the conversion result is pretty good though but the pulse always triggers the AINx_OV_ERR error flag (which we had to disable due to this) and thus we cannot detect if the ADC is overranging or not.

    We have already contacted you via the local representative several weeks ago but we are still stuck without an explanation or fix.

    Our measurement scheduler is such that we cannot use other than single_conversion mode although in our system, disabling the single_conversion does not seem to help much either. The only thing that seems to help is to run conversions continuously but that is not possible in our system.

    BR, Risto H.

  • 0
    •  Analog Employees 
    on Oct 29, 2020 5:14 AM 2 months ago in reply to Risto_H


    Are you using standard silicon? I would recommend to use the B-grade silicon as it has benefits over the standard part and it resolves the issues/anomaly in the settling issue at Gain=1. There will be some glitch at gain=1 because of internal cap directly connected to external load. The pre-charge reduces the glitch and settle quicker so the effect on the conversion is removed.



  • Hi Jellenie

    We are using the B-grade silicon in our design.

    I have studied the nature of the disturbance pulses a bit and found out that increasing the input capacitance suppresses the disturbance. The 10 nF anti-aliasing capacitor that is also used in the EV board is way too small in this respect. A 220 nF cap can suppress the peaking enough in most cases but it is still visible (and naturally 220 nF is not feasible in most cases). This tells me that it is unlikely that in this case there is a sampling capacitor or similar causing the trouble but rather some sort of glitch that momentarily connects the digital supply to the input. In our case this effect is perhaps amplified by the fact that our analog supplies are +2.6 V and -0.9 V. The digital supply is 3.3 V.

    As we already have raised this case through the local channel, I would have continued over there but somehow no one had recognized the similarity between this and our case which is why I wanted to raise the question here too.

    I wonder is there is any good workaround for the problem? Maybe using the internal sequencer to always make a quick dummy conversion from the internal temp sensor (or some other channel) and only then measure the desired channel?

    BR, Risto

  • 0
    •  Analog Employees 
    on Oct 29, 2020 9:20 AM 2 months ago in reply to Risto_H

    Is there also a chance that you have seen the considerations in selection of external RC at page 46 of the datasheet?

    So the error also dependent on the selected output data rate and the value of the external RC filter.

    But from what you are saying, you believed that this isn't the case, meaning that it is not a settling issue or a gain of 1 issue? Is that correct?

    And that is really pretty unusual as I haven't heard or experience this issue with the part itself. So my assumption is that it supposed to be related on how you used the part in your system/application board. 

    I can't really comment right now on how to solve this issue as I do not have a complete background on your application and design. But from my understanding is that the glitch is only happening after single conversion mode isn't it? And in this mode, the part performs single conversion and then placed in standby mode after the conversion. In standby mode, most blocks are powered down. Diagnostics can be enabled or disabled while in standby mode. However, any diagnostics that require the master clock (reference detect, undervoltage/overvoltage detection, LDO trip tests, memory map CRC, and MCLK counter) must be enabled when the ADC is in continuous conversion mode or idle mode; these diagnostics do not function if enabled in standby mode. Meaning you have to exit standby mode to monitor correct OV/UV detection. To exit standby mode, the AD7124-8 requires 130 MCLK cycles to power up and settle. Meaning, if you are converting a single channel In single conversion mode, I do not see the relevance in monitoring OV/UV as you have to switch to idle mode or continuous conversion mode to be able to detect it.

    Are you using multiple channels and use the sequencer in converting all of the channels? Meaning in single conversion mode all of the channels enabled are converted once, then I presume only the last conversion should have the glitch error issue if I will based it from your description. Isn't it? If that's the case then I think having a dummy conversion can solve this but it still depends on your target speed (output data rate as it will need additional settling and conversion time). And I don't think I really understand what might have causes this issue. Do you have a scope shot of the glitch, is it possible to capture this? I was just wondering what might have trigger this glitch at the end of conversion.