I've recently encountered a strange phenomenon in Single Conversion Mode. At the beginning of the new conversion strong interference appears at both pins of the first logical channel used. The input circuit is typical - differential mode anti-alias filter 2x10k + 10nF and 2x3n3 pair to system analog GND. The interference is in the form of positive pulse of about 100mV amplitude and about 50us of time and it's present at both pins of the logical channel (because of this, differential measurement is disturbed to a less extent). The disturbance comes from the inside of the IC, it's not present anywhere beyond the input circuit. The disturbance appears only at the beginning of the first conversion after the Standby phase after previous single conversion. If the ADC is configured to take some consecutive measurements, the first one, and only the first one is disturbed, no matter what logical channel is used. The disturbance is independent of the hardware channels used, one can "move" the disturbance to any pin pair, just by reconfiguring the first logical channel used in the sequence. The distrurbance is independent of the conversion config (filter, data rate etc). Burnouts are off.
Any idea how to get rid of this? Switching to continuous conversion (or conversion in pairs - with the first conversion "lost") would be a problem.
We released a B-grade of the AD7124-8 that includes a pre-charge buffer. This pre-charge buffer was added to reduce the settling time needed for the analog input to settle. ON the standard part, we…
In my understanding, it is only the first channel (Channel_0) has the issue? when you tried the second channel (Channel_1) or third channel (Channel_2) in the sequence with the same analog input pins you cannot see the disturbance? Can you clarify this? When you are not taking measurements, or does not select any channel, are you still seeing this issue? If you could share the register settings and as well as your measurement setup (block diagram or schematic) it would be helpful. Do you also have a scope shots of the above scenarios so I can easily visualize the issue? Are you using the evaluation board or your own design board? Have you check the supply/reference decoupling and grounding connections? Can you also perform noise test by shorting the inputs together and bias to some voltage (usually mid supply).
not exactly. The issue regards to first channel used in a sequence of measurements. More exactly it regards to any physical pins connected to this channel. Any channel can be affected - e.g. I use Channel_0 in some measurements, and Channel_4 ... Channel_7 sequence in another measurements, and affected channels are Channel_0 and Channel_4. Most of the experiments I've performed using channels 4-7, but I think channel number doesn't really matters. AD7124 always selects enabled channels in order of their numbers, so always the channel with lowest number is affected, regardless of hardware pins selected.
Example 1: chanel 4, 5, 6, 7 are enabled. Channel 4 is AIN7-AIN6, Channel 5 is AIN9-AIN8, Channel 6 is AIN11-AIN10, Channel 7 is AIN13-AIN12. Affected pins are: AIN7, AIN6.
Example 2: chanel 4, 5, 6, 7 are enabled. Channel 4 is AIN9-AIN8, Channel 5 is AIN7-AIN6, Channel 6 is AIN11-AIN10, Channel 7 is AIN13-AIN12. Affected pins are: AIN9, AIN8.
In fact, input circuits of AIN9-AIN8 pair is identical as AIN7-AIN6 and the disturbance is also the same. I've noticed: the higher input resistors of anti-alias filter and smaller capacitor, the higher the disturbance.
I use my own board, but input circuits are very similar to eval board. The ADC has 0-3V3 power supply and static input voltages at mentioned inputs is 1.5V. I strongly believe, everything is OK with my board.
I believe, the most important thing is measurement mode. I use "single sequence" mode, so after sequence of measurements ADC goes to some idle mode (automatically - I cannot prevent it, unfortunately). When new sequence starts, ADC has to exit from this idle mode and here the problem lies: the first enabled channel is selected, analog pins are connected by means of internal MUX and then something inside the ADC "powers up", creating the disturbance. The time interval from starting the measurement (CONTROL register write) to the disturbance is in the range of microseconds.
I'll provide some scope shots soon.
Important note: the disturbance appears only with GAIN = 1.
channel 2 is AIN7. Channel 3 is debug/trigger signal. The pulse is at the end of the SPI transaction writing CONTROL register. The ADC is in Idle state before the measurement.
CONTROL register settings:
ADC_CONTROL_POWER_MODE_FULL |ADC_CONTROL_MODE_CONTINUOUS_CONVERSION |ADC_CONTROL_SEND_STATUS_BYTE | ADC_CONTROL_CLK_SEL_EXTERNAL_614400HZ
CONFIG register settings (SETUP_4):
ADC_SETUP_BIPOLAR_OPERATION | ADC_SETUP_BURNOUT_OFF | ADC_SETUP_REF_PLUS_BUFFERED | ADC_SETUP_REF_MINUS_BUFFERED | ADC_SETUP_INPUT_PLUS_BUFFERED | ADC_SETUP_INPUT_MINUS_BUFFERED |ADC_SETUP_USE_EXTERNAL_REF_2 | ADC_SETUP_GAIN_1
(I don't remember if buffering settings are effective with Gain = 1)
External ref is 3V, DC bias at the AIN7: 1.5V
CHANNEL register settings (it's Channel_4 - first of enabled channels):
ADC_CHANNEL_ENABLE | ADC_CHANNEL_USE_SETUP_4 | ADC_CHANNEL_POSITIVE_IN_AIN7 | ADC_CHANNEL_NEGATIVE_IN_AIN6
We released a B-grade of the AD7124-8 that includes a pre-charge buffer. This pre-charge buffer was added to reduce the settling time needed for the analog input to settle. ON the standard part, we have seen a settling time anomaly at high output data rates whereby the first conversion is not fully settled within the allowed time for large resistive loads. The latest datasheet discusses this anomaly. Can you order some B-grade parts and confirm whether they resolve the disturbance issue.
Not good news. The grade B version also shows similar effect, although the pulse is about 20% less of amplitude.
Design flaw of the IC?
Let me confirm this with the product owner/designer and get back to you,