curious about ad7770 'CLK_QUAL_DIS' register.


I am using 7.68MHz for mclk.

And then i'm try to 'clock modulation' mclk.

Therefore, i'm try to disable 'CLK_QUAL_DIS' so that 'EXT_MCLK_SWITCH_ERR' is not set.

However, the datasheet says that the CLK_QUAL_DIS setting should be used when 'mclk < 265 kHz'.

I want to know if it is ok to disable 'CLK_QUAL_DIS' at 'mclk > 265 kHz'.

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[edited by: PCM at 8:43 AM (GMT 0) on 8 Aug 2019]