AD7770 questions.

Hi.

I have two questions about ad7770.

   1. how long time to start and finish the conversion?

       'sar' has timing data(conversion time) on the data sheet, but no 'delta-sigma'.

   2. When does 'MCLK Switch Error' occur?

      I am trying to adjust the conversion timing by  'external mclk' modulation.

      So, how long does it take for an error to occur after the mclk input is blocked?

Best Regards.

  • 0
    •  Analog Employees 
    on Aug 20, 2019 10:04 AM

    Hello ,

    The 'conversion time' is applicable to the SAR because it's the time from the CONVST pulse till that data point is available at the output, however Sigma-Delta is not so straightforward. Sigma-Delta is continuously converting and providing data at its output at the programmed ODR. So, the closest parameter to what you are looking for is the group delay, and it might directly depend on the decimation ratio programmed. The higher the DecRate, the longer it will take to post process the data after the modulator.

    For the MCLK Switch Error, it would only happen in power up, when the control is passed over from the internal clock (used during initialization) to the external clock (required to perform ADC conversions). Are you trying to change your master clock dynamically during operation? What's the objective by doing so? Wouldn't you prefer have a fixed MCLK and change the Sample-Rate-Converter on the fly?

    See more info on MCLK Switch Error here: https://www.analog.com/media/en/technical-documentation/application-notes/AN-1405.pdf

    Regards,

    Lluis.