Can we configure the AD7768-1 as an ADC with an adjustable sampling frequency?

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Can we configure the AD7768-1 as an ADC with an adjustable sampling frequency?

Can we directly switch the sampling frequency of the chip through the program? I mean don't change the external hardware device. Simply use the FPGA to input a command to the ADC via SPI .Because I see that the AD7768-1 provides three power modes and kinds of modulator and  filters.

  • Hi,

    There are 4 MCLK divide options that can be set via SPI which will directly change the sampling rate. The question is, do you want to change the sampling rate or the output data rate? The AD7768-1 is a Sigma-Delta ADC which is over-sampled. 

    The output data rate (ODR) can be adjusted by changing the MCLK_div setting and the decimation rate. The output data rates achievable in this scenario would be powers of two. For example, 256kSPS, 128kSPS, 64kSPS. If an alternative output data rate is needed you could also change the MCLK provided to the part.

    ODR = MCLK/(MCLK_DIV × Decimation Rate)



  • HI,

    Thanks for your reply!

      Some people wants me to use the AD7768-1 chip to make a collector that can select the sampling frequency.But I found that there is only a description of the ODR in the data sheet, not sampling frequency.So what is the correspondence between sampling frequency and ODR? if the requirement is that sampling frequency just be less than one-half of the ODR?

    And another question i want to ask is that,if its  make sense to do this  in your opinion.?

    Because I think that selecting the sampling frequency as a high frequency can still collect signals lower than the set frequency....


  • Hi Lizhe,

    The AD7768-1 is a Sigma-Delta ADC. The principal of operation is an over-sampled architecture followed by decimation and filtering. You can see more on how Sigma-Deltas work Here and also in the Theory of Operation section of the datasheet. 

    The sampling rate is determined by FMOD which is set by a combination of the MCLK and the internal divide set by MCLK_div. The MCLK is supplied by the user. The output data rate is also dependent on decimation rate which I have shown in my response above.

    The maximum input signal bandwidth the AD7768-1 can digitize depends on the output data rate and filter selected. To see how all this works I suggest taking a look at the filter tool which appears on the AD7768-1 product page. You can see how the MCLK, MCLK_div and decimation rate affect the output rate, SNR and power consumed.

    The AD7768-1 Product Page contains the Filter Model in the Tools and Simulations section. To be clear, the AD7768-1 can output data at rates as high as 1MSPS to as low as hundreds of Hz. 



  • Hi  Niall,

    Thank you very much for helping me solve this problem!


  • Hi  Niall,

    Thank you very much for your answer!

    There is another question I hope to get your help.

    When we operat  AD7768-1,if it works in the low power mode and using the sinc5 filter in the default?

    And how can I find out the default state after the chip is powered on  in the datasheet?