Can we configure the AD7768-1 as an ADC with an adjustable sampling frequency?

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Can we configure the AD7768-1 as an ADC with an adjustable sampling frequency?

Can we directly switch the sampling frequency of the chip through the program? I mean don't change the external hardware device. Simply use the FPGA to input a command to the ADC via SPI .Because I see that the AD7768-1 provides three power modes and kinds of modulator and  filters.

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  • Hi Lizhe,

    The AD7768-1 is a Sigma-Delta ADC. The principal of operation is an over-sampled architecture followed by decimation and filtering. You can see more on how Sigma-Deltas work Here and also in the Theory of Operation section of the datasheet. 

    The sampling rate is determined by FMOD which is set by a combination of the MCLK and the internal divide set by MCLK_div. The MCLK is supplied by the user. The output data rate is also dependent on decimation rate which I have shown in my response above.

    The maximum input signal bandwidth the AD7768-1 can digitize depends on the output data rate and filter selected. To see how all this works I suggest taking a look at the filter tool which appears on the AD7768-1 product page. You can see how the MCLK, MCLK_div and decimation rate affect the output rate, SNR and power consumed.

    The AD7768-1 Product Page contains the Filter Model in the Tools and Simulations section. To be clear, the AD7768-1 can output data at rates as high as 1MSPS to as low as hundreds of Hz. 

    Regards

    Niall

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