Can we configure the AD7768-1 as an ADC with an adjustable sampling frequency?

Ask for your helping.

Can we configure the AD7768-1 as an ADC with an adjustable sampling frequency?

Can we directly switch the sampling frequency of the chip through the program? I mean don't change the external hardware device. Simply use the FPGA to input a command to the ADC via SPI .Because I see that the AD7768-1 provides three power modes and kinds of modulator and  filters.

Parents
  • Hi,

    There are 4 MCLK divide options that can be set via SPI which will directly change the sampling rate. The question is, do you want to change the sampling rate or the output data rate? The AD7768-1 is a Sigma-Delta ADC which is over-sampled. 

    The output data rate (ODR) can be adjusted by changing the MCLK_div setting and the decimation rate. The output data rates achievable in this scenario would be powers of two. For example, 256kSPS, 128kSPS, 64kSPS. If an alternative output data rate is needed you could also change the MCLK provided to the part.

    ODR = MCLK/(MCLK_DIV × Decimation Rate)

    Regards

    Niall

Reply
  • Hi,

    There are 4 MCLK divide options that can be set via SPI which will directly change the sampling rate. The question is, do you want to change the sampling rate or the output data rate? The AD7768-1 is a Sigma-Delta ADC which is over-sampled. 

    The output data rate (ODR) can be adjusted by changing the MCLK_div setting and the decimation rate. The output data rates achievable in this scenario would be powers of two. For example, 256kSPS, 128kSPS, 64kSPS. If an alternative output data rate is needed you could also change the MCLK provided to the part.

    ODR = MCLK/(MCLK_DIV × Decimation Rate)

    Regards

    Niall

Children