Mochi,
Can you give me a bit more information regarding what the customer is trying to do with the WR/FSYNC line in terms of duplication? For example is the part in configuration mode or are you in Normal Mode, Reading Position? Are they trying to update another 1210 in the system at some point? Have they considered ensuring that during the WR pulse that the CS for the selected 1210 is pulled high?
As you stated attempting to write to a read only register should NOT cause any problems with the internal loop but to be 100% sure I'll verify this on the bench with some test code.
Sean
Hello, my customer has answered your question.
The part in configuration mode or are you in Normal Mode, Reading Position?The expected read only register is always written in normal mode.
Are they trying to update another 1210 in the system at some point?The RDC to be used together is from other companies.The device that AD2S1210 shares / WR with is EPROM.
Have they considered ensuring that during the WR pulse that the CS for the selected 1210 is pulled high?The idea was not considered.By changing the PLD program used for control, we may be able to switch CS when writing to a read only register.
Best regards
MOCHI,
If they can make the change to the PLD I think that is the best solution as the interface will certainly ignore any toggling on the WR\ pin.
In the mean time I will verify in the lab tomorrow that nothing unexpected happens if we try to toggle WR\ while in normal mode.