In Rev A of the AD2S1210 data sheet the description of clearing the fault register, says to refer to the "Reading from the AD2S1210 in Configuration Mode section." which refers to Figure 29 (Parallel Port Read Timing -- Configuration Mode) as well as Figure 31 (Parallel Port -- Clear Fault Register). In referring to both figures I noticed contradictory differences between Figure 31. and Figure 29. Bellow are questions about those differences. I've also included figure 29 and 31 for convenience.
- In figure 31. T2 spans between \CS low to \WR low. Instead should span between \CS low to \WR high, like figure 29.?
- T2's description: Delay \CS falling edge to \WR/\FSYNC rising edge
- In figure 31. T9 spans between the rising edge of \WR to the falling edge of \RD. Instead of being labeled T9 should it be T10 instead, like Figure 29.?
- T9's description: Delay between successive write cycles
- T10's description: Delay between rising edge of \WR/\FSYNC and falling edge of \RD
- In figure 31. T19 spans between \RD low to <FAULT DATA>. Should T19 instead be T12 like figure 29., and the existing T12 should be removed from Figure 31.?
- T19's description: Enable delay \RD/\CS low to data valid
- T12's description: Enable delay \RD low to data valid in configuration mode
