I'm working with an AD7766 design in which I just discovered the VREF is being supplied with a reference IC and amplifier circuit with a pretty big time constant (~1 second). Therefore, I'm seeing the VREF take about 6 seconds to 'fully settle' on power up.
In contrast, the AVDD settles pretty quickly (~500uS) after power is applied.
I've attached a graph illustrating what I'm describing.
My question is, am I risking any long term damage to the chip leaving the design this way? The board that this ADC is being used on is fairly mature and has a lot of usage as we're getting ready to move to production with it. I'd rather not change any characteristic of the VREF and it's filtering if I don't have to, due to the amount of testing, but will if I'm risking damage to the part.
After VREF has settled, will the subsequent reset (SYNC/PD line goes low, then high), address any oddities in the power supplies coming up at different rates?
Scope plot legend:
Orange = AVDD
Blue = VREF
Black = VIN+
Green = VIN-