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AD7766 Production
The AD7766/AD7766-1/AD7766-2 are high performance, 24-bit, oversampled SAR analog-to-digital converters (ADCs). The AD7766/AD7766-1/AD7766-2 combine the...
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AD7766 on Analog.com

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VREF rise time



		

			

									
					    agporsch
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on May 16, 2019 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    I'm working with an AD7766 design in which I just discovered the VREF is being supplied with a reference IC and amplifier circuit with a pretty big time constant (~1 second).  Therefore, I'm seeing the VREF take about 6 seconds to 'fully settle' on power up.
    

    In contrast, the AVDD settles pretty quickly (~500uS) after power is applied.
    

    I've attached a graph illustrating what I'm describing.
    

    My question is, am I risking any long term damage to the chip leaving the design this way? The board that this ADC is being used on is fairly mature and has a lot of usage as we're getting ready to move to production with it. I'd rather not change any characteristic of the VREF and it's filtering if I don't have to, due to the amount of testing, but will if I'm risking damage to the part.
    

    After VREF has settled, will the subsequent reset (SYNC/PD line goes low, then high), address any oddities in the power supplies coming up at different rates?
    

    Scope plot legend:
    

    Orange = AVDD
    

    Blue = VREF
    

    Black = VIN+
    

    Green = VIN-
    

    

     
    

    Thank you.
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			


				
	









	
      
	

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      •  Analog Employees  
      
            
			                            
                        
                on May 17, 2019 5:29 PM
            
            
					
      
	
      

		
		
      
					
      Hi agporsch,
      

      

      The vref input is typically a much slower input to power-up and settle, due to the larger capacitors on this node, so it is not unusual to see the longer rise time of this supply/input compared to the Avdd and Dvdd supplies. As long as you do not exceed the absolute maximum ratings as specified on page 8 of the AD7766 datasheet then no damage should occur. 
      

      However, I do see in the plot that the Vref and Vin+/- input are recorded as starting at -7V and -8V. If this is relative to the AGND or REFGND in the system then this would be a concern. The maximum negative voltage allowed on these pins is -0.3V relative to AGND.
      

      

      Regards,
      

      Stuart.
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
						
				
				
		
		
      
			
		
      
	
      

      

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                on May 20, 2019 5:29 PM
            
            
												
						in reply to StuartADI
					
									
        
	
        

		
		
        
					
        Thank you for the response. While I agree, due to the suggested placing of a 100uF cap on the VREF line, generally speaking, I would expected to see a 'larger' time constant.
        

        However, assuming a low impedance of the amp driving the VREF (say ~50 ohms), I would expect a time constant on the order of 5 milliseconds. An observed rise time of 6 seconds is, naturally, significantly longer, and just seemed a bit odd. I know where its occurring in my circuit, but was just trying to get a feel from AD, if that 'extreme' settle time is still OK.
        

        To clarify, the VREF+/- aren't starting at -7 and -8V, respectively. The scope shows a different axis for each plot. In this case, the green (VIN-) is layered on top of the black (VIN+). In both cases, those plots use the 2 vertical axes on far left of the plot, and it can be seen that they are at zero.
        

        Thanks again.
        
			
        

		
		
		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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