I'm looking to incorporate 2 AD7616 ADCs into my design, as I need 32 16-bit ADC channels at a minimum of 1Msps. I've read through the datasheet of the AD7616 a couple of times now, and it seems like the perfect fit, as it also incorporates input clamps, input buffering, internal precision referencing and reference buffering as well, nice!
The one issue I have is around interfacing of the two ADCs with my MCU, which is an ATSAME70Q21. This MCU does have a parallel interface, but it's only 8-bit so wouldn't be suitable for the parallel output of the AD7616 (I don't believe, happy to proven wrong if the 16-bit parallel output can be sent in two 8-bit chunks?), and as there is only one of them it wouldn't constitute a solution for both ADCs anyway. Similarly, the MCU has a QSPI-compatible interface, which would accommodate the full throughput capability of the AD7616 in serial 2-wire mode, but again it only has 1 QSPI interface so it wouldn't accommodate both ADCs.
Can you think of another approach which would allow for full throughput to be accommodated from both ADCs? I supposed I could use QSPI for one of the ADCs, and look to use some other means on the other. Would a 16-bit (or 8-bit if it could be read in chunks) parallel-in/serial-out shift register solution be possible?
Any input would be greatly appreciated!
I've just had a thought, can I use a shared clock on both ADCs from the QSPI interface, then use 2 of the QSPI data lines for 1 ADC and the other 2 data lines for the other ADC, then perform the required data rearranging in software?