AD7175-8 : number of oversample

Hi,

Based on the table you have provided, I am assuming that the customer is using the Sinc5+Sinc1 filter option. Is that correct?

Actually, the calculation above looks like simple and correct but this is not the actual timing calculation for the part. For AD717x, there's an extra delay time at the very first conversion. It's the setup time for the signal chain before the first conversion is available. It is always 68MCLKs for AD7175 but it varies from other parts. If sequencing is enabled or SINGLE_CYC=1 then it will only be the very first conversion that will have this delay and all subsequent conversion requires a settling time slightly shorter than the very first conversion. This is the settling time listed on table 19. I can send you through personal email regarding the settling time calculations so that you can calculate the correct oversampling ratio which include the delays when switching channels or when SINGLE_CYC=1.

Thanks,

Jellenie

Hello Jellenie,

Thank you for your support.

> Based on the table you have provided, I am assuming that the customer is using the Sinc5+Sinc1 filter option. Is that correct?

Yes, the customer is using Sinc5 + Sinc1 filter.

> If sequencing is enabled or SINGLE_CYC=1 then it will only be the very first conversion that will have this delay and all subsequent conversion requires a settling time slightly shorter than the very first conversion.

He set SINGLE_CYC to "1" and enabled sequencing to scan eight channels. (Differential input configuration)

> I can send you through personal email regarding the settling time calculations so that you can calculate the correct oversampling ratio which include the delays when switching channels or when SINGLE_CYC=1.

 I wish to know the calculations to explain the correct oversampling ratio to our customer.

Would you please send it to my e-mail address (suzuki-y@macnica.co.jp) ?

Best regards,

y-suzuki

Hi,

May I know the reason why the customer needs to know the oversampling internal with the chip? May I know the application or specific to the customer? I just need to clarify first to the product owner if the formula is open for customer release. For the mean time, Eval+ and Virtual Eval tool have the timing details. So the customer can play around to understand how the timing works at different configurations.

Thanks,

Jellenie

Hi,

Just to follow you up. I have talked with the product owner and she suggested to use the available filter excel model tool https://www.analog.com/media/en/engineering-tools/design-tools/ad7175_2_filter_model.xlsx to get the formula and as well as understand how the ODR, settling time was calculated.

1. Oversampling ratio is dependent on the filter choice and you will see this from the filter excel model (please see attached link above).

2. Since in your case, the customer is using sinc5+sinc1, so looking at the constant tab you see that for this filter the over sampling ratio is constant 32 for sinc5 which it give a maximum rate of 250ksps and will follow by a sinc1 averaging block which control the final ADC ODR. Thus, the formula needed to calculate ODR is as follows

ODR single channel free running for ODR>10ksps = Fmod/(SINC*AVG) where Fmod=Fclk/2 and Fclk=16MHz.

ODR multiple channel (single cycle settling = 1) for ODR <= 10ksps = [Fmod/(SINC*(AVG+4)+1)] where in +1 is the associated dead time when channel cycling and +4 enables the specific ODR to be achieved. If you see below, you get single cycle settling from ODRs of 10ksps and lower

3. In terms of the settling time, the settling time is the time required to generate a very first conversion. If single channel is used, the settling time is required for the first conversion and all subsequent conversions occur at selected output data rate. If multiple channels are enabled, the first conversion in the sequence requires a settling time mentioned above. The next conversions in the sequence requires a slightly shorter time than the settling time. The settling time still depends on the filter choice and selected ODR. The extra delay time at the very first conversion is the setup time for the signal chain before the first conversion is available. It is always 68MCLKs for AD7175 but it varies from other parts. Thus, the settling time for a very first conversion is as follows:

Tsettle 1st conversion = [(SINC*(AVG+4)+34)/Fmod] where in Fmod=Fclk/2 and Fclk is the Master clock of 16MHz. wherein +34 is a delay for the very first conversion which is equivalent to 68MCLKs.

The settling time for multiple channels enabled is as follows:

Tsettle multiple channels (SINGLE_CYC=1) = [(SINC*(AVG+4)+1)/Fmod] 

Thanks,

Jellenie

Hello Gellenie,

I'm sorry I couldn't reply to your previous question.
The customer has a issue that how to appeal the performance of his product to end customer.
I appreciate your attentive answer and explanation.
I'm going to inform it our customer.

Thanks a lot.

y-suzuki