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# AD7175-8 : number of oversample

Hello,

I have a question about number of oversample of AD7175-8 from a customer.
There is the comment which is the margin note of table-19 in the datasheet, is are following.

"The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate."

This customer need the precise oversample numbers to explain the specification of his product.
- "SING_CYC=1"
- multiple channels(8ch)
- ODR=125kSPS

I checked the relation between ODR and settling time.
In the table of below, the "Settling time" is same as 1/ODR x "Num of Oversamples" pricisely.
It  is not look like the "Settling time" was rounded.
All "number of oversamples" are divisible by "Settling time".

Then I would like to confirm the "Num. of Oversamples".
Is this "Num. of Oversamples", which is in below table, right ?

ODR of Multi-Ch        Settling time    Num. of Oversamples
50,000                      20 us                     160
41,667                      24 us                     192
31,250                      32 us                     256
27,778                      36 us                     288
20,833                      48 us                     384
17,857                       56 us                    448
12,500                       80 us                    640
10,000                     100 us                    800
5000                     200 ss                 1,600
2500                      400 us                 3,200
1000                       1.0 ms                8,000
500                       2.0 ms              16,000
397.5                   2.516 ms         20,128
200                      5.0 ms              40,000
100                       10 ms              80,000
59.92                 16.67 ms      133,360
49.96                 20.016 ms    160,128
20                       50.0 ms        100,000
16.66                 60.02 ms      480,160
10                     100 ms           800,000
5                      200 ms       1,600,000
* "Num. of Oversamples" = "Settling time"/ODR

Best regards,

y-suzuki

## Top Replies

• Hi,

Based on the table you have provided, I am assuming that the customer is using the Sinc5+Sinc1 filter option. Is that correct?

Actually, the calculation above looks like simple and correct but this is not the actual timing calculation for the part. For AD717x, there's an extra delay time at the very first conversion. It's the setup time for the signal chain before the first conversion is available. It is always 68MCLKs for AD7175 but it varies from other parts. If sequencing is enabled or SINGLE_CYC=1 then it will only be the very first conversion that will have this delay and all subsequent conversion requires a settling time slightly shorter than the very first conversion. This is the settling time listed on table 19. I can send you through personal email regarding the settling time calculations so that you can calculate the correct oversampling ratio which include the delays when switching channels or when SINGLE_CYC=1.

Thanks,

Jellenie

• Hello Jellenie,

> Based on the table you have provided, I am assuming that the customer is using the Sinc5+Sinc1 filter option. Is that correct?

Yes, the customer is using Sinc5 + Sinc1 filter.

> If sequencing is enabled or SINGLE_CYC=1 then it will only be the very first conversion that will have this delay and all subsequent conversion requires a settling time slightly shorter than the very first conversion.

He set SINGLE_CYC to "1" and enabled sequencing to scan eight channels. (Differential input configuration)

> I can send you through personal email regarding the settling time calculations so that you can calculate the correct oversampling ratio which include the delays when switching channels or when SINGLE_CYC=1.

I wish to know the calculations to explain the correct oversampling ratio to our customer.

Best regards,

y-suzuki

• Hi,

May I know the reason why the customer needs to know the oversampling internal with the chip? May I know the application or specific to the customer? I just need to clarify first to the product owner if the formula is open for customer release. For the mean time, Eval+ and Virtual Eval tool have the timing details. So the customer can play around to understand how the timing works at different configurations.

Thanks,

Jellenie

• Hi,

Just to follow you up. I have talked with the product owner and she suggested to use the available filter excel model tool https://www.analog.com/media/en/engineering-tools/design-tools/ad7175_2_filter_model.xlsx to get the formula and as well as understand how the ODR, settling time was calculated.

1. Oversampling ratio is dependent on the filter choice and you will see this from the filter excel model (please see attached link above).

2. Since in your case, the customer is using sinc5+sinc1, so looking at the constant tab you see that for this filter the over sampling ratio is constant 32 for sinc5 which it give a maximum rate of 250ksps and will follow by a sinc1 averaging block which control the final ADC ODR. Thus, the formula needed to calculate ODR is as follows

ODR single channel free running for ODR>10ksps = Fmod/(SINC*AVG) where Fmod=Fclk/2 and Fclk=16MHz.

ODR multiple channel (single cycle settling = 1) for ODR <= 10ksps = [Fmod/(SINC*(AVG+4)+1)] where in +1 is the associated dead time when channel cycling and +4 enables the specific ODR to be achieved. If you see below, you get single cycle settling from ODRs of 10ksps and lower

3. In terms of the settling time, the settling time is the time required to generate a very first conversion. If single channel is used, the settling time is required for the first conversion and all subsequent conversions occur at selected output data rate. If multiple channels are enabled, the first conversion in the sequence requires a settling time mentioned above. The next conversions in the sequence requires a slightly shorter time than the settling time. The settling time still depends on the filter choice and selected ODR. The extra delay time at the very first conversion is the setup time for the signal chain before the first conversion is available. It is always 68MCLKs for AD7175 but it varies from other parts. Thus, the settling time for a very first conversion is as follows:

Tsettle 1st conversion = [(SINC*(AVG+4)+34)/Fmod] where in Fmod=Fclk/2 and Fclk is the Master clock of 16MHz. wherein +34 is a delay for the very first conversion which is equivalent to 68MCLKs.

The settling time for multiple channels enabled is as follows:

Tsettle multiple channels (SINGLE_CYC=1) = [(SINC*(AVG+4)+1)/Fmod]

Thanks,

Jellenie

• Hello Gellenie,