About the Filter Register setting of AD7708

Hello,

In the single conversion mode of AD7708,
if t_ADC is shortened by 80msec by the setting of Mode Register,
Specifically, which period will be reduced by 80msec?
Is it correct to understand that the period from when a single conversion is instructed
by the mode register to when RDY is asserted is reduced by 80msec?

Regards,
Tatsu

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  • +1
    •  Analog Employees 
    on Apr 15, 2019 7:37 AM

    Hi,

    Apologies, but I'm a bit confused with the question. However, When single conversion mode is selected,the conversion requires the complete settling time of the filter. The settling time will be dependent on selected data rate (fADC) and if chop is enabled or disabled. So meaning it is not exactly the same ratio of time reduction when you changed the fADC.

    Thanks,

    Jellenie

Reply
  • +1
    •  Analog Employees 
    on Apr 15, 2019 7:37 AM

    Hi,

    Apologies, but I'm a bit confused with the question. However, When single conversion mode is selected,the conversion requires the complete settling time of the filter. The settling time will be dependent on selected data rate (fADC) and if chop is enabled or disabled. So meaning it is not exactly the same ratio of time reduction when you changed the fADC.

    Thanks,

    Jellenie

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