I'm using the AD7770 Eval Board. The Main Supply of the board is from the 9V external Wall Adapter and I want to get ADC data to Altera FPGA board through J1 header ( SPI mode)
However, after the power up the DRDY signal is always at LOW state. I also try to reset the board by apply RESET signal sequence describe in Fig4, AD7770 Datasheet, but the DRDY state is still the same.
My question is: Do I have to do any extra step to get the DRDY pulse , or the DRDY pulse is present right after the power up of the ADC ? How can I know the Eval board and the AD7770 is supplied power properly ?