Similar question to that of DavidLee a few months ago. The datasheet has me confused concerning how to transfer the data from the chip.
Can I simply pulse !CNV high for 30ns, wait 220ns, then issue 16 (or 32 or 64) clock pulses and read the data?
The description of the DC2395 evaluation board seems to indicate that the clock must run continuously. If it must, then I'm still confused (even after reading the replies to DavidLee's question) about how to know when the conversion data is available.
Yes, CNV high for 30ns, wait 220ns followed by clock pulses to read the data is all that is necessary.
Can you explain what about the data sheet/ timing diagrams you find confusing?
The continuous clock used in the DC2395A is used by the FPGA to generate the CNV and clock signals. If you look with an oscilloscope at the CNV and SCK signals applied directly to the LTC2324 you will see they are similar to the timing diagrams in the data sheet.
Thanks for the quick reply. I guess the main two items of confusion are about Table 2 Conversion Frequency for Various I/O modes (frequencies seem wrong) and page 24 of the datasheet under the /CNV Timing description where it states that the conversion process is timed by the SCK input clock, but the conversion sounds like it proceeds and finishes in 220ns without any clock.
The LTC2324-16 data sheet is being revised. Table 2 will be changed as shown below
Thanks for pointing out the error in the CNV Timing paragraph. That will be fixed as well.