The AD7767/AD7767-1/AD7767-2 are high performance, 24-bit, oversampled SAR analog-to-digital converters (ADCs). The AD7767/AD7767-1/AD7767-2 combine the...
AD7767 on Analog.com
I will use AD7767 DAISY-CHAIN MODE
I'd like to confirm only that a DRDY signal becomes Low first, so SCLK isn't kept.
A DRDY signal won't be Low only AD7767 (A), is SCLK necessary?
（SCLK is being always input in figure 37, but is it necessary?）
The number of SCLK falling edges that occur when DRDY is low must match the number of devices in the chain multiplied by 24 as shown in the figure. You can either provide continuous SCLK or start providing…
Thank you for your answer