is AD7767 SCLK need

I will use AD7767 DAISY-CHAIN MODE

I'd like to confirm only that a DRDY signal becomes Low first, so SCLK isn't kept.

A DRDY signal won't be Low only AD7767 (A), is SCLK necessary?

(SCLK is being always input in figure 37, but is it necessary?)

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  • 0
    •  Analog Employees 
    on Feb 26, 2019 11:27 AM

    Hi,

    The number of SCLK falling edges that occur when DRDY is low must match the number of devices in the chain multiplied by 24 as shown in the figure. You can either provide continuous SCLK or start providing the SCLK after DRDY and CS low as long as you provide the required number of SCLKs and also meet the required timing and SLCK frequency.

    Please refer to Choosing the SCLK frequency and also timing specifications of the datasheet.

    Thanks,

    Jellenie

Reply
  • 0
    •  Analog Employees 
    on Feb 26, 2019 11:27 AM

    Hi,

    The number of SCLK falling edges that occur when DRDY is low must match the number of devices in the chain multiplied by 24 as shown in the figure. You can either provide continuous SCLK or start providing the SCLK after DRDY and CS low as long as you provide the required number of SCLKs and also meet the required timing and SLCK frequency.

    Please refer to Choosing the SCLK frequency and also timing specifications of the datasheet.

    Thanks,

    Jellenie

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