AD7172-2 CHANNELREGISTERS

Hi

I have deposited AD 7172 - 2 questions from my customers.

Customer is evaluating AD7172-2. They are using 3 channels from CH 0 to CH 2.
The customer noticed the behavior which he did not expect.
The AD7172-2 occasionally outputs data as follows.
1 ch → 0 ch → 1 ch → 2 ch → 0 ch → 1 ch
0 ch → 2 ch → 0 ch → 1 ch → 2 ch → 0 ch
I and the customer think that this is different from the data sheet.

Is this normal behavior?
Can you give me some advice? Please.
Best regards
Parents
  • +1
    •  Analog Employees 
    on Feb 20, 2019 3:24 AM

    Hi,

    Did the customer timing out or monitoring the conversion through DRDY pin or RDY bit in the status register while reading and also enable the DATA+STAT to know which channel corresponds the conversion? When multiple channels are enabled, a complete settling time is required for every channel switch. This is to allow the digital filters and modulator to settle when switching channels. Thus, the rate at which data is available (DOUT/RDY pulls low) for multiple channels would be dependent on the corresponding settling time for the output data rate(ODR) set. The user must then read the conversion result while the ADC converts the next enabled channel; otherwise, the new conversion result is lost. So, it is really recommended to monitor the DOUT/RDY pin to check if valid conversion is available. Can you stop reading back the conversions and just monitor the DOUT/RDY pin to determine if it is pulsing at the corresponding settling time?

    May I ask also for the register map settings and as well as the scope shot of the digital interface?

    Thanks,

    Jellenie

Reply
  • +1
    •  Analog Employees 
    on Feb 20, 2019 3:24 AM

    Hi,

    Did the customer timing out or monitoring the conversion through DRDY pin or RDY bit in the status register while reading and also enable the DATA+STAT to know which channel corresponds the conversion? When multiple channels are enabled, a complete settling time is required for every channel switch. This is to allow the digital filters and modulator to settle when switching channels. Thus, the rate at which data is available (DOUT/RDY pulls low) for multiple channels would be dependent on the corresponding settling time for the output data rate(ODR) set. The user must then read the conversion result while the ADC converts the next enabled channel; otherwise, the new conversion result is lost. So, it is really recommended to monitor the DOUT/RDY pin to check if valid conversion is available. Can you stop reading back the conversions and just monitor the DOUT/RDY pin to determine if it is pulsing at the corresponding settling time?

    May I ask also for the register map settings and as well as the scope shot of the digital interface?

    Thanks,

    Jellenie

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