AD7175-8 Multiple Channel Read

Hey,

I am still learning how to properly communicate with this ADC with an STM32F4. I cant seem to figure out how to read the channels separately. 

When i put voltage on AIN0 and read data from chan_1 and chan_2, the 2 channels show the same data.

For testing i am doing the below

AD7175_ReadData(&AD7175_regs[CH_Map_1]);
chan1 = spiRxBuf[1];
chan1 <<= 8;
chan1 |= spiRxBuf[2];
chan1 <<= 8;
chan1 |= spiRxBuf[3];

HAL_Delay(100);

AD7175_ReadData(&AD7175_regs[CH_Map_2]);
chan2 = spiRxBuf[1];
chan2 <<= 8;
chan2 |= spiRxBuf[2];
chan2 <<= 8;
chan2 |= spiRxBuf[3];

HAL_Delay(100);

Full code is available on github

https://github.com/maxhohenlohe/AD7175-8/blob/master/Src/main.c

Any suggestions are greatly appreciated.



Added MCU
[edited by: maxhohenlohe at 6:36 AM (GMT 0) on 23 Dec 2018]
  • 0
    •  Analog Employees 
    on Dec 28, 2018 3:30 AM

    Hi,

    Are you monitoring the RDY pin or RDY bit in the status register while reading and also enable the DATA+STAT to know which channel corresponds the conversion? When multiple channels are enabled, a complete settling time is required for every channel switch. This is to allow the digital filters and modulator to settle when switching channels. Thus, the rate at which data is available (DOUT/RDY pulls low) for multiple channels would be dependent on the corresponding settling time for the output data rate(ODR) set. The user must then read the conversion result while the ADC converts the next enabled channel; otherwise, the new conversion result is lost. So, it is really recommended to monitor the DOUT/RDY pin to check if valid conversion is available. Can you stop reading back the conversions and just monitor the DOUT/RDY pin to determine if it is pulsing at the corresponding settling time?

    Thanks,

    Jellenie

  • Thanks for the quick response. Yes i can see the pulse, and if i trigger the status register i can see when each of the channels is ready to read.

    I am wanting to split the channels into separate variables, Id assume the best way to do so is with DATA_STAT and reading the channel info from the data read. I tried using timing after DOUT/RDY pulls low, and reading from the status register separately but this is still mixing the channels at times.

    I have the Interface_Mode_Register set to 0x0040 which i believe enables the DATA_STAT in the data, but i can not figure out where the DATA_STAT info is stored within.

    Attached is a sniff of a chan_0 read with the DATA_STAT enabled.

  • 0
    •  Analog Employees 
    on Jan 14, 2019 5:48 AM in reply to maxhohenlohe

    Hi,

    The status is placed after the data, so data register + status register. You need additional 8 clock cycles for the status register.

    Thanks,

    Jellenie